Why Low Power Matters
Why battery life, heat and cost make power a design constraint in every modern chip, from phones to data centres.
Low power is not only about batteries. Power turns into heat, heat limits performance and reliability, and every watt has to be delivered through package pins and a power grid that cost money. This lesson looks at those pressures one at a time, with numbers, so you can explain why a team spends months on power.
Battery life: energy, not just power
A battery stores energy, so what matters is power multiplied by time. A phone battery of 5,000 mAh at 3.85 V holds about 19.25 Wh. Most of the day a phone sits idle with its screen off, so standby power decides how long it lasts in a drawer.
Battery energy = 5.0 Ah × 3.85 V = 19.25 Wh
Standby at 50 mW → 19.25 / 0.050 ≈ 385 hours
Standby at 30 mW → 19.25 / 0.030 ≈ 640 hours
Cutting 20 mW of standby power (mostly leakage and always-on logic)
adds more than ten days of standby time. That is why leakage matters.For active work the useful idea is race to idle: finishing a task quickly at a higher voltage and then power gating can use less energy than running slowly for longer, because leakage is paid for every microsecond the block stays on. Which strategy wins depends on how much of the power is leakage: the more a block leaks, the more it pays to finish fast and switch off.
Heat: the thermal ceiling
All the power a chip draws ends up as heat, and silicon has a maximum junction temperature, typically around 105 to 125 °C depending on the product. A phone has no fan, so its SoC can sustain only a few watts before the case gets uncomfortably hot and the operating system throttles the clocks. A server chip has heat sinks and airflow, but its package still has a thermal design power (TDP) it cannot exceed.
Temperature also feeds back into power. Leakage rises roughly exponentially with temperature, so a hot chip leaks more, which makes it hotter. Designs with a lot of leakage have to be checked for this thermal runaway at the worst corner.
Reliability
- Electromigration: high current density slowly moves metal atoms in wires and vias until they open or short. Its lifetime falls sharply with both current and temperature, so higher power shortens chip life.
- Aging (NBTI, HCI): transistor threshold voltages drift over years of stress, faster at high temperature and voltage, which slows the chip down in the field.
- IR drop: more current means more voltage lost across the power grid, which slows cells and can cause timing failures that STA at nominal voltage never saw.
Cost
Power costs money even when nobody sees it. More current needs more supply bumps and package pins, wider power grids that take routing tracks from signals, bigger voltage regulators, more decoupling capacitors, and better cooling. In a data centre the electricity and cooling bill over a chip's life can exceed the chip's price, which is why accelerators are compared on performance per watt.
The toolbox at a glance
The savings below are typical ranges reported for real designs. The actual number depends heavily on the design and its workload, so treat them as orders of magnitude, not promises.
| Technique | Targets | Typical saving | Applied in |
|---|---|---|---|
| Clock gating | Dynamic (clock and registers) | 20-40% of dynamic | RTL style, synthesis |
| Multi-Vt | Leakage | 10-30% of leakage, often more | Synthesis, ECO |
| Operand isolation | Dynamic (datapaths) | 5-15% of block dynamic | RTL, synthesis |
| Power gating | Leakage of an idle block | Up to about 95% of that block's leakage | UPF, PD |
| DVFS | Dynamic and leakage | Up to about 50% at low-performance points | Architecture, UPF, software |
| Retention registers | Enables power gating without losing state | Makes deep sleep practical | UPF, special cells |
A strong interview answer ties power to a product. "In a phone the constraint is standby energy and skin temperature, so I would focus on leakage and power gating. In an AI accelerator it is the thermal envelope at full load, so I would focus on dynamic power: clock gating, data gating and DVFS."
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