Retention Registers

Power gating a block removes its leakage, but it also wipes every flip-flop inside. When the block wakes up it has to be reset and reconfigured, which costs time and energy. Retention registers solve this: they keep their value through power-off using a small always-on storage element, so the block can resume where it left off.

How a retention flop is built

A retention flip-flop is a normal flop plus a small latch, often called a balloon or shadow latch, that is powered from the always-on supply. The main flop runs on the switchable supply and does the normal work. Before power-off, a save signal copies the flop's value into the balloon latch. After power returns, a restore signal copies it back.

Some libraries use a live-slave design instead, where the flop's own slave latch stays on the always-on supply and simply holds its value. Either way, the cell has two supply pins, a save and restore control (sometimes a single retain pin), and a larger footprint than a plain flop, typically one and a half to two times the area.

The power-down and power-up sequence

The exact order is set by the power controller's specification, but a typical sequence looks like this.

Going to sleep

1. Stop the clock to the domain, so no flop changes during the save.
2. Assert isolation on the domain's outputs.
3. Assert save: every retention flop copies its value into its always-on latch.
4. Turn off the power switches. The domain's supply collapses; the retention latches keep their values on the always-on supply.

Waking up

1. Turn the power switches back on and wait for the power-good acknowledge.
2. Assert restore: every retention flop reloads its saved value.
3. Release isolation.
4. Restart the clock.

Three rules never change whatever the order: the clock is stopped during save and restore, isolation is active whenever the domain is not fully powered and restored, and restore happens only after the supply is stable.

Which registers to retain

Retaining every flop is expensive: more area, more always-on leakage, more always-on routing for the save and restore signals. Designs use selective retention and keep only state that is costly or impossible to rebuild.

Large memories are handled differently: many SRAM macros have their own retention mode that lowers the array voltage just enough to keep the data while cutting the periphery's power.

Worked example: is retention worth it?

A block wakes up about 100 times per second. Without retention, each wake-up needs a software routine that rewrites 2,000 configuration bits and takes 50 µs at 20 mW of active power. With retention of those 2,000 bits, restore takes one clock cycle, but the balloon latches leak all the time. The numbers below are illustrative.

Without retention: re-init energy = 50 µs × 20 mW  = 1.0 µJ per wake-up
                   × 100 wake-ups per second       = 100 µW average

With retention:    2,000 balloon latches × ≈10 nW  = 20 µW always-on leakage
                   restore energy                  ≈ negligible

Retention wins here (20 µW vs 100 µW) and wakes up 50 µs faster.
With only 1 wake-up per second, re-init costs just 1 µW, and
retention's 20 µW of leakage would lose.

Writing it in UPF

set_retention ret_cpu -domain PD_CPU \
    -retention_supply_set SS_AON \
    -elements {u_cpu/u_csr u_cpu/u_pc} \
    -save_signal    {cpu_save high} \
    -restore_signal {cpu_restore high}

# Synthesis maps the listed registers to retention flops from the
# library. The rest of PD_CPU uses ordinary flops and loses its state.