Level Shifters & Isolation Cells

Power domains create boundaries, and signals crossing those boundaries need help. A level shifter fixes signals that cross between different voltages. An isolation cell fixes signals that come out of a domain that may be switched off. This lesson explains why each is needed, how they work, and how UPF tells the tools where to put them.

Level shifters: why a "1" is not always a 1

Suppose a 0.8 V domain drives an inverter in a 1.1 V domain. The driver's logic 1 is 0.8 V. At the receiver, the PMOS source is at 1.1 V, so with 0.8 V on its gate it still sees a gate-to-source voltage of about 0.3 V. That can be close to its threshold, so the PMOS is not fully off. The result is a weak output, extra delay and a static current flowing through the receiver the whole time the signal is high. At a large enough voltage gap the receiver may not even switch reliably.

A low-to-high level shifter solves this with a circuit powered by both supplies, commonly a pair of cross-coupled PMOS transistors on the high supply driven by NMOS inputs from the low domain. Because it needs both supplies, it has an extra supply pin and is placed where both are available, usually at the boundary on the destination side.

Going from high to low is easier: a buffer on the low supply can usually accept a higher input voltage. Many flows still insert high-to-low shifters so the crossing is characterised and timed properly, and to protect thin gate oxides when the voltage gap is large.

Isolation: what an off domain drives

When a domain is powered off, its outputs do not sit neatly at 0. They float somewhere between the rails and drift as the domain's supply collapses. A floating input on a powered gate can turn on both its PMOS and NMOS at once, drawing short-circuit current, and can be read as random logic values. An isolation cell sits on each output of the switchable domain and forces it to a known value while the domain is off.

• Clamp to 0: an AND-type cell. The output is the data AND the inverted isolation enable.
• Clamp to 1: an OR-type cell, for signals whose safe value is high.
• Latch-based: holds the last value the signal had before isolation, for the rare case where neither 0 nor 1 is safe.

Choosing the clamp value

The clamp value is a functional decision, not a physical one. Pick the value that means "nothing is happening" to the receiver. A request or valid signal clamps to 0 so the always-on logic never sees a false request. An active-low reset or active-low interrupt clamps to 1 so it stays inactive. Getting this wrong produces exactly the bug isolation was meant to prevent.

Where isolation cells live

The isolation cell must stay powered while the source domain is off, so it takes its supply from an always-on supply. It is usually placed in the receiving domain or the parent, not inside the domain being switched off. The isolation enable signal itself comes from the always-on power controller.

Timing of the isolation enable

Isolation must be switched on before the domain's supply starts to fall, and switched off only after the domain is powered, stable and restored. If isolation is released too early, the receiver sees whatever garbage the waking domain produces. The power controller sequences this, and power-aware simulation checks it.

Worked example

A CPU domain runs at 0.8 V and can be switched off. The always-on fabric runs at 0.9 V. The CPU sends irq (active high) and bus_valid to the fabric, and the fabric sends wake_n to the CPU.

Writing it in UPF

# Outputs of the switchable CPU domain: isolate, clamp to 0,
# powered from the always-on supply set, placed in the parent
set_isolation iso_cpu_out -domain PD_CPU \
    -applies_to outputs \
    -isolation_supply_set SS_AON \
    -clamp_value 0 \
    -isolation_signal cpu_iso_en -isolation_sense high \
    -location parent

# Signals that must idle high get their own strategy
set_isolation iso_cpu_n -domain PD_CPU \
    -elements {u_cpu/irq_n} \
    -isolation_supply_set SS_AON -clamp_value 1 \
    -isolation_signal cpu_iso_en -isolation_sense high

# Level shifters on the same boundary
set_level_shifter ls_cpu_out -domain PD_CPU \
    -applies_to outputs -rule low_to_high -location parent
set_level_shifter ls_cpu_in -domain PD_CPU \
    -applies_to inputs -rule high_to_low -location self

Synthesis reads these strategies and inserts the cells. Where both a level shifter and an isolation cell apply to the same signal, the tool can use a single enable level shifter cell.