Overview
Why power is a first-class design constraint in modern chips, and the techniques this path covers, from clock gating to UPF.
Every chip has a power budget, and on most modern designs it is as hard a limit as the clock frequency. A phone SoC has to fit inside a few watts or it overheats in your hand. A data centre accelerator has to fit inside the watts its package and cooling can remove. An IoT sensor has to live for years on a coin cell. This path teaches the techniques engineers use to hit those budgets, and where in the flow each one is applied.
Where the power goes
The power a CMOS chip draws splits into three parts. Two of them happen only when signals switch; the third happens all the time.
| Component | What causes it | Formula | Main knobs |
|---|---|---|---|
| Dynamic (switching) | Charging and discharging every wire and gate capacitance when a signal toggles | P = α · C · V² · f | Clock gating, operand isolation, lower V and f |
| Short-circuit | For a moment during each transition both the PMOS and NMOS conduct | Grows with slow input slews | Keep transitions sharp (max transition limits) |
| Static (leakage) | Current that flows through transistors that are supposed to be off | P = I_leak · V | High-Vt cells, power gating, lower V |
In the dynamic formula, α is the activity factor (the fraction of clock cycles in which a node toggles), C is the switched capacitance, V is the supply voltage and f is the clock frequency. The clock network is the busiest net on the chip: it toggles every cycle, so its α is 1, and it often burns a third or more of all dynamic power. That is why clock gating is the first technique in this path.
Leakage used to be a rounding error. From about the 90 nm node onwards it became a large share of total power, because thinner oxides and lower threshold voltages let more current slip through transistors that are switched off. Leakage also rises steeply with temperature, so it is always signed off at the hot corner.
Worked example: which knob matters most?
Take a block with an effective switched capacitance of 2 nF, running at 1 GHz from 0.9 V, with an average activity factor of 0.15, and 20 mA of leakage current.
Dynamic = α · C · V² · f
= 0.15 × 2 nF × (0.9 V)² × 1 GHz
= 0.15 × 2e-9 × 0.81 × 1e9 = 0.243 W (243 mW)
Leakage = I_leak × V = 20 mA × 0.9 V = 18 mW
Total ≈ 261 mW
Option A: clock gating cuts average activity from 0.15 to 0.10
Dynamic = 0.10 × 2e-9 × 0.81 × 1e9 = 162 mW (dynamic 33% lower)
Option B: lower the supply by 10%, from 0.90 V to 0.81 V
V² goes from 0.81 to 0.656, so dynamic = 197 mW (19% lower)
Leakage also drops (less voltage, and less DIBL)Two lessons fall out of this. First, voltage is the strongest lever because it appears squared, which is why dynamic voltage and frequency scaling (DVFS) exists. Second, the techniques stack: a real design uses clock gating and multi-Vt and voltage scaling and power gating together, each attacking a different term.
What this path covers
| Lesson | Attacks | Where it is applied |
|---|---|---|
| Clock gating (ICG) | Dynamic power of idle registers and the clock tree | RTL coding style, inserted by synthesis |
| Multi-Vt | Leakage of cells on non-critical paths | Synthesis and post-route ECO |
| Power domains and voltage islands | Architecture: which blocks share a supply | Specification and UPF |
| Level shifters and isolation | Signals crossing between domains | UPF, inserted by synthesis |
| Power gating (MTCMOS) | Leakage of whole idle blocks | UPF, switch cells placed in PD |
| Retention registers | Keeping state through power gating | UPF, special flops |
| UPF | Describing all of the above once, for every tool | The whole flow |
| DVFS, power analysis, power states | Runtime voltage scaling and signoff | Architecture, signoff |
When asked "how would you reduce power?", do not list techniques at random. Split the answer by component. Dynamic: clock gating, operand isolation, DVFS. Leakage: multi-Vt, power gating, lower voltage. Then say which one you would apply first for the block in question, and why.
Power numbers are only as good as the activity that produced them. A power report built on a default toggle rate can be off by a factor of two or more. Signoff power uses switching activity from real simulations (SAIF or VCD/FSDB files). The Power Estimation lesson later in this path covers that.
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