Every VLSI concept, one clear explanation away

The window before the clock edge where data must be stable.

The window after the clock edge where data must stay stable.

Timing margin on a path, positive passes, negative fails.

The clock arrival-time difference between two flip-flops.

Cycle-to-cycle variation in the clock edge position.

Margin set aside for skew, jitter and modeling error.

Modeling on-chip variation, pessimistic derates to statistical.

The constraints that define clocks, I/O timing and exceptions.

A path never timed because it cannot functionally happen.

A path allowed more than one clock cycle to complete.

Proving a chip meets timing without simulating every input.

The loop of fixing setup and hold across every corner.

Placing macros and setting core/die area, the first physical step.

Building the power grid that feeds every cell.

Positioning standard cells for timing and routability.

Building the real buffered clock network.

Turning logical connections into real metal.

Too many wires competing for too few routing tracks.

Voltage lost across the power grid's resistance.

Metal atoms migrating under high current density over time.

Checking the layout obeys the foundry's manufacturing rules.

Proving the layout matches the intended netlist.

Register-transfer level, describing hardware behaviour in HDL.

Turning RTL into a gate-level netlist.

The gate-level description of a design after synthesis.

Logic whose output depends only on the present inputs.

Logic with memory, outputs depend on state and the clock.

An edge-triggered one-bit storage element.

A level-sensitive storage element.

Switching off the clock to idle logic to save power.

Complementary MOS, the transistor logic every chip is built from.

An application-specific integrated circuit, custom-built for one job.

A reprogrammable logic device, flexible but slower than an ASIC.

The pre-characterised logic-gate library the tools place and route.

Hard blocks like memories and IP placed during floorplanning.

Process, voltage, temperature, the conditions timing signs off across.

The manufacturing technology generation (28nm, 7nm…).

The stacked interconnect layers wires are routed on.