Project 1 · OpenLane / LibreLane · Sky130

Take a real RISC-V CPU from RTL to GDSII

Watch every step on video, then do it yourself: from an empty PC to a signoff-clean layout of a real CPU. Each episode comes with the commands written out to copy, the reports explained, and a certificate at the end that anyone can verify.

19
HD video episodes
46
lessons in total
~13 h
of guided work
1
verifiable certificate
Free preview, no sign-in needed.1080p HDEnglish captions0.5× to 2× speedCommands written out to copy

What you get

  • 19 HD video episodes (1080p) with English captions and speed control
  • Full RTL to GDSII flow using OpenLane on a real design
  • Step by step synthesis, floorplan, placement, CTS, routing, signoff
  • Capstone project: take a real RISC-V CPU (picorv32) from RTL to GDSII
  • Starts from an empty PC: VirtualBox and Ubuntu 22.04 setup included
  • Run Yosys and OpenSTA by hand, and read every report
  • Error labs: break the design on purpose, then find and fix the problem
  • Tcl scripts and config files included
  • Final exam and a verifiable certificate
  • A finished GDSII you can open and inspect
  • Bonus: Interview Bootcamp and Fresher Pack, included free

Video episodes

19 episodes · about 39 min of video

Every lesson of the project opens with its video. Below each one, every step is written out: the commands to copy, the reports to read, and what to do when something fails.

Part 1 · 12 episodes · 24 min

Build the RISC-V CPU, RTL to GDSII

  1. Episode 01Welcome, and the map of the whole journeyFree1:17
  2. Episode 02Prepare Windows and install VirtualBox2:26
  3. Episode 03Create the Ubuntu 22.04 VM and install Ubuntu3:21
  4. Episode 04Install LibreLane and prove it with the smoke test2:30
  5. Episode 05Meet the CPU: picorv32, its timing target and its config2:18
  6. Episode 06Synthesis by hand with Yosys0:54
  7. Episode 07Run the full flow, and read the synthesis stage2:22
  8. Episode 08Floorplan and placement, and seeing them in the OpenROAD GUI3:14
  9. Episode 09Clock tree synthesis and routing0:46
  10. Episode 10Static timing analysis with OpenSTA2:23
  11. Episode 11Signoff: DRC, LVS and antenna checks1:03
  12. Episode 12The finished chip in KLayout, and your certificate1:20

Part 2 · 7 episodes · 15 min

Your Own Standard Cell

  1. Episode 13Your own inverter: open it in Magic and fix its DRC errors2:25
  2. Episode 14Extract a SPICE netlist and simulate the inverter1:29
  3. Episode 15From layout to library cell: tracks, neighbours, ports and LEF1:55
  4. Episode 16Characterize the inverter and write its Liberty file1:29
  5. Episode 17Build picorv32 with your own inverter, and sign it off4:03
  6. Episode 18Fix slack before layout: synthesis strategy, OpenSTA and an ECO1:56
  7. Episode 19Clock tree lab: buffer choice, skew and post-CTS timing1:38

Theory and reference lessons

9 modules · 27 lessons
  1. Course Overview

The certificate

Certificate of completion

Your Name

OpenLane RTL-to-GDS · passed the final exam

SP-OL-20260924-4821 · siliconpath.in/verify

What you leave with

A signoff-clean GDSII of a real CPU, your own timing and DRC reports, the scripts, and a resume line you can defend in an interview.

Who wrote it

A working physical design engineer, using the same checks a signoff team runs. Questions go to the community and get answered.

Who it is for

Built for ECE graduates, PD freshers, and VLSI students who want to run a real open-source flow end to end. If you have never taken a design to GDSII before, this is the cleanest way to do it on your own machine.

Questions

A Windows PC with at least 12 GB of RAM, 4 CPU cores and 80 GB of free disk space. 16 GB of RAM and 100 GB free is recommended for the RISC-V capstone, because the virtual machine takes 8 GB. A PC already running Ubuntu 22.04 works too.

₹999+ 2 courses free