Back-end path

Physical Design

The full backend flow as a working PD engineer runs it. You start from a synthesized netlist and take it to a clean GDSII, learning floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure along the way.

11
lessons
1 h 56 min
of reading
Intermediate
level
Free
every lesson

Lessons

11 lessons · 1 h 56 min
  1. 01Introduction to Physical DesignHow physical design turns a synthesized netlist into a manufacturable GDSII layout: floorplan, placement, power, clock tree and routing.2 min
  2. 02FloorplanningThe anatomy of a chip die, and how to choose die size, core utilization, macro placement and the power grid in the floorplan.7 min
  3. 03Power PlanningBuilding the power distribution network: pads, core ring, stripe mesh, M1 rails and via arrays; IR drop, electromigration, decaps and power domains.13 min
  4. 04PlacementGlobal, legalization and detailed placement: rows and sites, timing- and congestion-driven placement, density, blockages and place-opt.14 min
  5. 05Clock Tree Synthesis (CTS)How CTS builds a real, balanced clock network: topologies (H-tree, spine, mesh), skew, latency, useful skew and the hold it exposes.18 min
  6. 06RoutingGlobal and detailed routing: the metal stack, tracks, vias, congestion, NDR and shielding, crosstalk and antenna, DRC/LVS and ECO routing.16 min
  7. 07Physical VerificationSignoff PV: DRC (spacing/width/enclosure), LVS device-by-device compare, the antenna effect and its fixes, ERC and DFM, and the tape-out gate.12 min
  8. 08PD Tool KnowledgeThe place-and-route tools: what a PnR tool runs, Cadence Innovus and Synopsys ICC2/Fusion command flows, OpenROAD/OpenLane, and how to compare them.8 min
  9. 09Congestion Analysis and FixesWhy routing fails, and how to find the cause9 min
  10. 10IR Drop and Power IntegrityWhen the power grid cannot keep up9 min
  11. 11The ECO FlowMaking small, surgical late-stage changes8 min