Physical Design
The full backend flow as a working PD engineer runs it. You start from a synthesized netlist and take it to a clean GDSII, learning floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure along the way.
Introduction to Physical Design
Physical Design converts a synthesized gate-level netlist into a manufacturing-ready GDS layout, determining the physical placement, power, clock, and routing o
Floorplanning
Anatomy of a Chip Die - Every Term Explained
Power Planning
The positive voltage rail. At 28nm ≈ 0.9–1.05V, at 5nm ≈ 0.65–0.8V. Every cell's PMOS transistors connect here. When VDD wire has resistance, current causes a v
Placement
What Is a Standard Cell Row? (The Grid Cells Sit In)
Clock Tree Synthesis (CTS)
Key CTS Concepts - From Scratch
Routing
Metal Layers - Why Multiple Layers Exist
Physical Verification
Verifies the layout satisfies all foundry manufacturing rules (spacing, width, enclosure, density). Zero DRC violations required for tape-out. Tool: Calibre DRC
PD Tool Knowledge
PD Tool Knowledge
Congestion Analysis and Fixes
Why routing fails, and how to find the cause
IR Drop and Power Integrity
When the power grid cannot keep up
The ECO Flow
Making small, surgical late-stage changes