Front-end path

Clock Domain Crossing

Almost every chip has multiple clocks, and signals crossing between them cause some of the hardest bugs in digital design. This path teaches clock domain crossing from the ground up: why metastability happens and cannot be timed away, the two-flop synchronizer, why buses need gray code, asynchronous FIFOs, handshake and pulse synchronizers, reset synchronization, and how CDC is actually verified.

8
lessons
1 h 8 min
of reading
Intermediate
level
Free
every lesson

Lessons

8 lessons · 1 h 8 min
  1. 01Why Clock Domain Crossing MattersWhat breaks when a signal crosses clocks7 min
  2. 02Metastability, ExplainedWhy it happens and why you can only manage it8 min
  3. 03The Two-Flop SynchronizerThe standard fix for a single-bit crossing8 min
  4. 04Buses and Gray CodeWhy you cannot just synchronize a bus bit by bit9 min
  5. 05The Asynchronous FIFOThe standard way to move data between clocks11 min
  6. 06Handshake and Pulse SynchronizersCrossing pulses and arbitrary data safely9 min
  7. 07Reset SynchronizationAsserting async, removing it synchronously8 min
  8. 08CDC Verification and Common MistakesHow CDC is checked, and the traps to avoid8 min