Static Timing Analysis
STA is how you prove a chip will run at speed without simulating every input. This path builds your timing intuition from the ground up: setup and hold, clock definitions, uncertainty, multicycle and false paths, on-chip variation, and full signoff with PrimeTime.
Introduction to STA
Key Terms - Defined Before We Go Further
Timing Path Types
STA analyzes 4 fundamental path types in digital circuits. Every timing path has a startpoint (port or FF clock pin) and endpoint (FF data pin or output port).
Setup & Hold Slack Analysis
Data arrives before required time. Extra margin available. Setup: Slack = +0.3ns means 300ps of timing margin. Design passes. No action needed.
Clock Domain Crossing (CDC)
CDC occurs when a signal crosses from one clock domain to another. This creates a risk of metastability - the output of a flip-flop remains at an indeterminate
On-Chip Variation (OCV) & AOCV
Real silicon has spatial and temporal variation in process, voltage, and temperature (PVT). OCV models capture that cells on the same die can behave differently
Multi-Mode Multi-Corner (MMMC)
Modern designs must meet timing across multiple operating modes (functional, scan, standby) AND multiple PVT corners simultaneously. MMMC analysis runs all comb
Synopsys PrimeTime
PrimeTime (PT) is the industry-standard sign-off STA tool. It uses accurate parasitic data (SPEF) from the extracted layout for final timing certification.
Cadence Tempus
Cadence Tempus
Timing Closure Techniques
Fixing Setup Violations
Latch Borrowing
Latch borrowing (also called time borrowing) is a timing technique where a slow logic stage borrows time from the next pipeline stage using level-sensitive latc
CRPR: Removing Clock Pessimism
Why hold paths show violations that are not real
Graph-Based vs Path-Based Analysis
Recovering margin the fast analysis throws away
Crosstalk and Signal Integrity
When a neighbouring net changes your timing