Back-end path

Synthesis

Logic synthesis is where RTL becomes gates. This path covers how Design Compiler and Genus read your RTL, apply constraints, map to a standard cell library, and optimize for timing, area, and power. You learn to write clean SDC and read synthesis QoR like an engineer who has shipped silicon.

11
lessons
1 h 41 min
of reading
Beginner
level
Free
every lesson

Lessons

11 lessons · 1 h 41 min
  1. 01Introduction to SynthesisWhat logic synthesis does, the key terms it uses, and how RTL becomes an optimized gate-level netlist of standard cells.3 min
  2. 02Detailed Synthesis FlowRTL to gate-level netlist stage by stage: read, elaborate (GTECH), logic optimization, technology mapping, post-map optimization, and formal equivalence.12 min
  3. 03Synopsys Design Compiler (DC)The Design Compiler flow: libraries, read/elaborate, constrain, compile_ultra, report and write out; topographical mode and Fusion Compiler.7 min
  4. 04Cadence GenusThe Genus flow as explicit generic to mapped to optimized stages, its common UI with Innovus, and iSpatial physical synthesis.6 min
  5. 05Timing Constraints (SDC)The SDC timing contract: clocks (create_clock, generated, virtual), input/output delay and the I/O budget, uncertainty and latency (pre/post-CTS), exceptions, clock groups and case analysis.14 min
  6. 06Optimization TechniquesTrading timing, area and power across the three optimization passes: restructuring, sizing, buffering, cloning, resource sharing, clock gating, multi-Vt and DRC fixing.12 min
  7. 07Quality of Results (QoR)Reading QoR across timing (WNS/TNS/WHS + the slack histogram), area, power and design-rule legality, how to read report_qor, and fixing QoR in priority order.10 min
  8. 08Retiming: Moving Registers to Balance LogicRelocating flops across logic to shorten the critical path9 min
  9. 09Hierarchy: Ungroup, Flatten, and Boundary OptimizationWhen to dissolve module boundaries and when to keep them9 min
  10. 10Power-Aware Synthesis: Clock Gating and Multi-VtCutting dynamic power with gating and leakage with cell swaps10 min
  11. 11DFT and Scan-Aware SynthesisBuilding testable logic by stitching flops into scan chains9 min