Front-end path

Design Verification

Verification is the largest job in chip design, and this path teaches it from the ground up. You begin with why verification exists and a simple self-checking testbench, then learn the SystemVerilog features and object-oriented basics that everything rests on, constrained random stimulus, functional coverage, assertions, and finally the big picture of UVM and how its pieces fit together. Plain explanations, real examples, no assumed background.

14
lessons
2 h 15 min
of reading
Beginner
level
Free
every lesson

Lessons

14 lessons · 2 h 15 min
  1. 01What Verification Really IsWhy finding bugs before silicon is its own profession7 min
  2. 02A Simple TestbenchDrive inputs, check outputs, and make it self-checking8 min
  3. 03SystemVerilog for VerificationThe data types and features that make testbenches powerful9 min
  4. 04Object-Oriented BasicsClasses and objects: the foundation UVM is built on10 min
  5. 05Randomization and ConstraintsLet the tool invent test cases you never thought of10 min
  6. 06Functional CoverageMeasuring whether you actually tested enough9 min
  7. 07AssertionsRules the design must never break, checked automatically9 min
  8. 08UVM - The Big PictureWhy the standard framework looks the way it does11 min
  9. 09Building a UVM TestbenchA walkthrough of the pieces and how to keep growing10 min
  10. 10UVM Sequences and the SequencerHow stimulus is generated, arbitrated, and layered11 min
  11. 11UVM RAL: The Register LayerVerifying registers by name, with a mirror you can trust11 min
  12. 12Advanced Constrained Randomsolve-before, dist, soft constraints, and shaping the spread10 min
  13. 13Advanced SVA: Sequences and PropertiesMulti-cycle behavior, implication, and avoiding vacuous pass11 min
  14. 14RTL LintRTL lint explained: the static checks that catch bugs before simulation and synthesis, common lint rules (latches, sensitivity, multi-driver, width), lint vs simulation vs formal, and how to handle waivers.9 min