Back-end path

Physical Verification

Before a design tapes out it has to pass physical verification. This path covers Design Rule Checking, Layout Versus Schematic, antenna and ERC checks. You learn what each check is protecting against, how to read violation reports, and how to fix the common ones without breaking timing.

12
lessons
1 h 24 min
of reading
Intermediate
level
Free
every lesson

Lessons

12 lessons · 1 h 24 min
  1. 01OverviewThe signoff checks that prove a layout can be manufactured and matches its netlist: DRC, LVS, ERC, antenna and density.1 min
  2. 02PV Flow OverviewThe physical verification checks run at signoff, the failure each one catches, and the order they are run in.6 min
  3. 03DRC: Design Rule CheckHow DRC checks layout geometry against the foundry rules for width, spacing and enclosure, and why those rules exist.8 min
  4. 04LVS: Layout vs. SchematicHow LVS extracts a netlist from the layout and compares it with the schematic to catch shorts, opens and mismatches.8 min
  5. 05ERC: Electrical Rule CheckERC catches electrical issues that DRC and LVS miss. A layout can be DRC-clean and LVS-clean but still have electrical errors that cause chip malfunction.6 min
  6. 06Antenna CheckWhy metal connected to a gate collects charge during plasma etching, how the antenna ratio is checked, and how violations are fixed.6 min
  7. 07Metal Fill & Density RulesWhy chemical mechanical polishing needs uniform metal density, how density rules are checked, and how metal fill fixes them.6 min
  8. 08PV Tool KnowledgeCalibre from Siemens and IC Validator from Synopsys: what each signoff verification tool does and how they compare.6 min
  9. 09Physical Verification Interview QuestionsPhysical verification interview questions with model answers on DRC, LVS, ERC, antenna and density checks.6 min
  10. 10Multi-Patterning and Coloring ChecksWhy one mask cannot print a layer, and how coloring is verified10 min
  11. 11DFM and Lithography HotspotsBeyond pass or fail: rules that protect yield10 min
  12. 12LVS Debugging MethodologyA systematic way to trace shorts, opens, and mismatches11 min