Power Gating (MTCMOS)

Power gating cuts the supply to a block that is idle, so its transistors stop leaking. It is the most powerful leakage technique there is, often removing more than 90% of the block's leakage, and the most involved to implement, because the block loses its state and needs isolation, sequencing and careful power-up. The switches are built from high-Vt transistors, which is where the name MTCMOS (multi-threshold CMOS) comes from.

Header and footer switches

A power switch is a large transistor placed between the real supply and the block's local supply, which is called the virtual supply because it only exists when the switch is on.

The switch transistors use high Vt, often with a thicker oxide, so that the switch itself leaks very little when it is off. A leaky switch would defeat the purpose.

Sizing the switches

When the block is on, all of its current flows through the switches, and their on-resistance creates a voltage drop that adds to the grid's IR drop. Switches are therefore sized for the block's peak current with a small drop budget, often a few percent of the supply.

Block peak current            = 200 mA
Allowed drop across switches   = 20 mV   (about 2% of 0.9 V)
Required total on-resistance   = 20 mV / 200 mA = 0.1 Ω

If one switch cell has an on-resistance of 400 Ω,
switches needed ≈ 400 / 0.1 = 4,000 cells in parallel,
spread evenly across the domain so no region starves.

Rush current and the daisy chain

Turning a block on means charging all of its capacitance from zero. If every switch closes at once, the inrush current is huge, and it pulls down the supply for the neighbouring blocks that are still running, which can make them fail timing or even lose state. The standard fix is to close the switches gradually.

• Switches are connected in a daisy chain: the enable ripples from one switch cell to the next, so they turn on one after another over tens of nanoseconds or more.
• Many designs use two chains: a first chain of weak "trickle" switches that charge the virtual supply slowly, then a second chain of strong switches that close once the voltage is nearly up.
• The end of the chain returns an acknowledge to the power controller, which waits for it before it restores state and releases isolation.

Worked example: the break-even time

Power gating is not free. Every sleep and wake cycle costs energy: recharging the block's capacitance, running the save and restore sequence, and the controller's own activity. Gating only pays off if the block stays off long enough for the leakage saved to exceed that cost.

Block capacitance on the virtual supply   = 5 nF
Energy drawn to recharge it: C · V²       = 5 nF × (0.9 V)² ≈ 4 nJ
Save, restore and control overhead        ≈ 2 nJ
Total overhead per sleep/wake cycle       ≈ 6 nJ

Leakage saved while off                   = 5 mW
Break-even time = 6 nJ / 5 mW             = 1.2 µs

Idle periods shorter than about 1.2 µs cost more energy than they save.
In practice, power managers gate only when they expect a much longer idle
time, because wake-up latency also matters.

Coarse and fine grain

Coarse-grain gating puts one set of switches in front of a whole block, such as a CPU core, and is the norm in SoCs. Fine-grain gating builds a switch into individual cells, which avoids the big switch network but costs area in every cell and is rare in general digital design.

In the physical design flow

• The switch cells are placed in columns or a grid across the domain after the power grid is built, connecting the always-on supply on upper metal to the virtual supply on the cell rails.
• The daisy chain enable and acknowledge are routed as always-on signals.
• IR drop analysis includes the switch resistance, and a separate power-up analysis checks the rush current and the time to reach the good voltage.