Specialized path

Design for Test

Every manufactured chip must be tested for physical defects, and Design for Test is the logic and methodology that makes it possible. This path covers testability from the ground up: verification versus test, fault models and coverage, scan design, automatic test pattern generation, scan compression, memory BIST, and boundary scan with JTAG, plus where DFT fits in the flow.

8
lessons
1 h 4 min
of reading
Intermediate
level
Free
every lesson

Lessons

8 lessons · 1 h 4 min
  1. 01Why Design for Test ExistsCatching manufacturing defects in real silicon7 min
  2. 02Fault Models and CoverageHow we model physical defects as testable faults8 min
  3. 03Scan DesignTurning every flip-flop into a test point10 min
  4. 04ATPG: Generating the PatternsHow test patterns are created automatically9 min
  5. 05Scan CompressionCutting test time and test data7 min
  6. 06Memory BISTTesting on-chip memories from the inside8 min
  7. 07Boundary Scan and JTAGTesting the connections between chips8 min
  8. 08DFT in the Design FlowWhere DFT fits, and the rules that make it work7 min