Multi-Threshold Voltage (Multi-Vt)

A standard cell library usually comes in several threshold voltage (Vt) flavours with the same functions, footprints and pins. A NAND2 exists as a high-Vt, a standard-Vt and a low-Vt version, and often an ultra-low-Vt one too. Multi-Vt optimisation uses slow, low-leakage cells wherever timing allows and fast, leaky cells only where it must.

The physics in two sentences

A transistor that is off still conducts a small subthreshold current, and that current falls exponentially as the threshold voltage rises: roughly ten times less leakage for every 70 to 100 mV of extra Vt at room temperature. A higher Vt also leaves less gate overdrive (V minus Vt), so the transistor switches more slowly.

So the trade is lopsided in your favour: a high-Vt cell might be 20 to 40% slower but leak ten times less. Most paths in a design have spare slack, so most cells can afford to be slow.

The flavours

Exact numbers depend on the process and library. The ratios below are illustrative and relative to an LVT cell.

Because the flavours share footprints, swapping one for another is a legal change at any stage, even after routing. That makes Vt swapping one of the cheapest timing and leakage ECOs there is. At FinFET nodes, libraries often add a second knob, channel length variants, which trade speed for leakage in the same way.

Worked example: leakage recovery

A block of 200,000 cells, all SVT, leaks 10 mW at the hot corner. After timing analysis, 80% of the cells turn out to have enough slack to become HVT, which in this library leaks four times less. Closing a few critical paths needs 5% of the cells to become LVT, which leaks four times more than SVT.

All SVT:                              10.0 mW

80% → HVT:   0.80 × 10 mW / 4           =  2.0 mW
15% stay SVT: 0.15 × 10 mW              =  1.5 mW
 5% → LVT:   0.05 × 10 mW × 4           =  2.0 mW
Total                                   =  5.5 mW   (45% less leakage)

Note that the 5% of LVT cells leak as much as all 80% of HVT cells.
Every LVT cell has to earn its place.

The flow

1. Synthesis starts from HVT and SVT cells, with LVT restricted or capped, so the tool uses fast cells only where the netlist cannot meet timing otherwise.
2. Place and route optimisation may swap cells to faster flavours to fix timing after real wire delays appear.
3. After routing, a signoff ECO pass (for example PrimeTime fix_eco_power) swaps every cell that has spare slack back to a lower-leakage flavour, checked against all timing corners.
4. Leakage is signed off at the worst leakage corner, usually fast process and high temperature.

# Design Compiler: cap the share of low-Vt cells
set_attribute [get_libs *lvt*] default_threshold_voltage_group LVT -type string
set_multi_vth_constraint -lvth_groups {LVT} -lvth_percentage 5
compile_ultra
report_threshold_voltage_group

# PrimeTime (signoff ECO): trade slack for leakage on every corner
fix_eco_power -pattern_priority {HVT SVT LVT}
write_changes -format icctcl -output vt_swap.tcl