UPF: Unified Power Format

RTL describes what a design does, but not how it is powered. The Unified Power Format (UPF, IEEE 1801) is a separate file, written in Tcl syntax, that describes the power intent: which supplies exist, how the design is split into domains, which domains can switch off, and where isolation, level shifting and retention are needed. Every tool in the flow reads the same UPF, so the power architecture is defined once and checked everywhere.

Why a separate file

Before UPF, each tool had to be configured for power by hand, and nothing guaranteed that simulation, synthesis, place and route and STA agreed. Keeping power intent out of the RTL also means the same RTL can be reused in chips with different power architectures. Cadence's earlier Common Power Format (CPF) served the same role; today UPF is the common standard across tools.

The building blocks

A complete example

The design has an always-on top level and a CPU domain that can be switched off. Both run at 0.9 V from the same regulator, so no level shifters are needed. If the CPU had its own voltage, you would add set_level_shifter strategies at the same boundary.

set_design_top soc_top

# 1. Supplies coming into the chip, and the switched CPU supply
create_supply_port VDD
create_supply_port VSS
create_supply_net  VDD
create_supply_net  VSS
create_supply_net  VDD_CPU_SW
connect_supply_net VDD -ports VDD
connect_supply_net VSS -ports VSS

# 2. Supply sets: the power/ground pairs each domain uses
create_supply_set SS_AON -function {power VDD}        -function {ground VSS}
create_supply_set SS_CPU -function {power VDD_CPU_SW} -function {ground VSS}

# 3. Power domains
create_power_domain PD_TOP -include_scope -supply {primary SS_AON}
create_power_domain PD_CPU -elements {u_cpu} -supply {primary SS_CPU}

# 4. The header switch that makes PD_CPU switchable
create_power_switch sw_cpu -domain PD_CPU \
    -input_supply_port  {vin  VDD} \
    -output_supply_port {vout VDD_CPU_SW} \
    -control_port       {en   cpu_pwr_en} \
    -on_state           {on_s  vin {cpu_pwr_en}} \
    -off_state          {off_s {!cpu_pwr_en}}

# 5. Isolation: clamp CPU outputs to 0 while it is off
set_isolation iso_cpu -domain PD_CPU -applies_to outputs \
    -isolation_supply_set SS_AON -clamp_value 0 \
    -isolation_signal cpu_iso -isolation_sense high -location parent

# 6. Retention for the CPU's control state
set_retention ret_cpu -domain PD_CPU -retention_supply_set SS_AON \
    -elements {u_cpu/u_csr} \
    -save_signal {cpu_save high} -restore_signal {cpu_restore high}

# 7. Power states of the CPU supply
add_power_state SS_CPU -state ON  {-supply_expr {power == FULL_ON && ground == FULL_ON}}
add_power_state SS_CPU -state OFF {-supply_expr {power == OFF}}

Reading it line by line

• Steps 1 and 2 declare the supplies. VDD_CPU_SW is the virtual supply that only exists when the switch is on.
• Step 3 puts everything in the always-on PD_TOP by default and moves the u_cpu instance into PD_CPU, which is powered by the switched supply set.
• Step 4 says the switch connects vin to vout when cpu_pwr_en is high. The power controller in PD_TOP drives that signal.
• Step 5 isolates every output of PD_CPU, using cells powered from SS_AON so they stay alive while the CPU is off.
• Step 6 maps the CSR block's flops to retention cells that save on cpu_save and restore on cpu_restore.
• Step 7 declares which supply states are legal, which the tools use to decide where isolation and level shifting are required. The Power States lesson later in this path builds the full power state table.

UPF through the flow

Teams usually keep a golden UPF written by the architects alongside the RTL. Implementation tools write out their own UPF after inserting cells, and that version travels down the flow with the netlist.