Blog
Notes on physical design, timing, and the EDA tools you use every day.
Understanding Setup and Hold Time Violations in PrimeTime
Setup and hold are the two halves of one question: did the data arrive at the flop at the right time. Here is how to read both in PrimeTime, and why hold is the one that should scare you.
Read →ICC2 Floorplanning: Where Most Engineers Go Wrong
A surprising number of backend problems are floorplan problems wearing a disguise. These are the macro placement and channel mistakes I see most often in ICC2.
Read →What is CTS and Why Does It Matter
Clock tree synthesis turns your ideal clock into a real one, and that is where hold violations are born. A plain explanation of skew, latency, and why CTS changes your timing.
Read →Timing Closure at 7nm: Key Differences from 28nm
Closing timing at 7nm is not 28nm with smaller numbers. Variation, crosstalk, and via resistance all change the game. Here is what actually shifts.
Read →How to Read a PrimeTime Timing Report
A timing report is a story about one path. Once you know how to read it line by line, debugging any violation becomes a matter of following the trail.
Read →What is Setup Time in VLSI?
Setup time is the window before the clock edge where data must be stable. A plain explanation with the equation, a worked example, and how setup violations are fixed.
Read →What is Hold Time in VLSI?
Hold time is the window after the clock edge where data must stay stable, and it is the violation that should worry you most. The equation, why it ignores the clock period, and how it is fixed.
Read →OCV vs AOCV vs POCV Explained
Three ways to model on-chip variation, each less pessimistic than the last. What OCV, AOCV, and POCV mean, how they differ, and which one advanced nodes use.
Read →Floorplanning in VLSI, Explained
Floorplanning is the first physical step and the one that decides whether the rest of the flow is easy or miserable. Die and core area, macro placement, utilization, and power planning, explained simply.
Read →Routing in VLSI, Explained
Routing turns logical connections into real metal. A plain explanation of global versus detailed routing, metal layers and directions, special-net rules, and why congestion is usually an upstream problem.
Read →Timing Closure Explained
Timing closure is a loop you run until setup and hold are clean at every corner. Constraints, MMMC analysis, closing setup then hold, and finishing with ECOs, the way engineers actually run it.
Read →Physical Design Interview Questions and Answers
The physical design questions that come up again and again, with the answers a working engineer would give. Flow, utilization, skew, CTS, congestion, IR drop, antenna, and DRC versus LVS.
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