Clock Gating (ICG)

Clock gating stops the clock to registers that do not need to change. It is the most widely used dynamic power technique because the clock is the most active signal on the chip: it toggles every cycle, drives every flip-flop, and runs through a large tree of buffers. When a register's value will not change, every clock edge it receives is wasted energy in the flop and in the clock buffers that feed it.

From an enable to a gated clock

A register that loads only when an enable is high is written in RTL like this. Without clock gating, synthesis builds it as a flip-flop with a multiplexer in front that feeds the old value back when the enable is low. The flop still sees every clock edge; it simply reloads its own value.

// Written once; synthesis decides how to build it
always @(posedge clk)
  if (en) data_q <= data_d;

// Without clock gating:  mux feedback, the flop clocks every cycle
//   data_q <= en ? data_d : data_q;
// With clock gating:     the mux is removed and an ICG cell drives
//   the flops' clock pins only in cycles where en is high

With clock gating turned on, the tool removes the feedback multiplexers and inserts an integrated clock gating (ICG) cell that passes the clock only when the enable is high. You do not write a gated clock by hand in RTL. Hand-gated clocks are a classic source of glitches and of paths that STA cannot time properly, so the normal rule is: write enables, and let synthesis insert ICG cells.

Why the ICG has a latch inside

The obvious gate is an AND of the clock and the enable. It fails because the enable comes from logic and can change at any time. If the enable rises or falls while the clock is high, the AND output produces a shortened pulse or a glitch, which can clock the downstream flops falsely.

An ICG for rising-edge flops fixes this with a latch that is transparent while the clock is low. The enable passes through the latch during the low phase and is frozen while the clock is high, so the AND gate only ever sees a stable enable during the high phase. The output is either a full clean pulse or nothing.

Libraries provide ICGs as single characterised cells rather than a latch and a gate placed separately. That way the latch-to-AND timing is guaranteed and the cell has proper setup and hold arcs on its enable pin. Most ICGs also have a test enable pin (often called SE or TE) that forces the clock on during scan shift so every flop can be tested.

The clock gating check

Because the enable must be stable around the clock edge, STA checks it like data into a flop. The ICG's library model has a setup and a hold requirement on the enable pin. For discrete gating logic, PrimeTime infers a clock gating check or you set one with set_clock_gating_check.

After clock tree synthesis these checks are often tight. The ICG sits near the root of its branch, so it receives the clock early, while the flops that generate the enable sit at the leaves and receive it late. The enable path therefore loses the latency difference between the two points, which eats into setup margin. Placing ICGs closer to the flops they gate, or cloning them, is the usual fix.

Worked example: is gating worth it?

Consider a bank of 2,000 flip-flops that only load new data 10% of the time, clocked at 1 GHz. The numbers below are illustrative, not from a specific library.

Clock energy per flop per cycle (pin + local wire)  ≈ 1.5 fJ
Ungated:  2,000 × 1.5 fJ × 1 GHz                    = 3.0 mW

Gated in groups of 32 flops → 63 ICG cells
Flops now clock 10% of cycles: 3.0 mW × 0.10        = 0.3 mW
ICG overhead, 63 cells × ≈5 fJ × 1 GHz              ≈ 0.3 mW
Total                                               ≈ 0.6 mW  (about 80% saved)

Bonus: the clock buffers downstream of each ICG also stop toggling.
Gating a single flop would cost more (one ICG) than it saves.

That last line is why tools have a minimum bit width for gating. An ICG costs area and its own clock pin power, so gating a one or two bit register can increase power. Four to eight bits is a common minimum.

Inserting clock gating in synthesis

# Design Compiler
set_clock_gating_style -sequential_cell latch \
                       -positive_edge_logic integrated \
                       -minimum_bitwidth 4 \
                       -max_fanout 32
compile_ultra -gate_clock
report_clock_gating            ;# gated vs ungated registers

# Genus
set_db lp_insert_clock_gating true
set_db lp_clock_gating_min_flops 4
syn_generic
syn_map
report_clock_gating

Levels of clock gating

• Register level (fine grain): inferred by synthesis from enables, as above. Covers most of the design automatically.
• Block level (coarse grain): one gate near the clock root turns off the clock to a whole block, such as an idle accelerator. Saves the entire clock tree of that block and is controlled by a power manager or software.
• Multi-stage: the tool merges common enables so one upstream ICG gates several downstream ICGs, saving more of the tree.