Learning paths

Learn the whole chip-design flow

15 paths and 154 lessons, every one free. Follow a path in order, or jump to any topic. Finish a path to earn a certificate anyone can verify.

128 STA interview questions

Not sure where to start?

Pick the job you want. Each track orders the paths for it.

Role trackPhysical Design EngineerFloorplans blocks and builds the power grid. Places cells and builds the clock tree.See the track Role trackSTA EngineerWrites and reviews SDC constraints. Analyses timing across modes and corners.See the track Role trackDesign Verification EngineerBuilds SystemVerilog and UVM testbenches. Writes constrained-random tests and assertions.See the track

Foundations

The logic and the language every chip starts from.

Digital Electronics11 lessons · 71 minNumber systems, gates, Boolean algebra, K-maps, and sequential logic, the foundation under every chip.BeginnerBoolean AlgebraK-Maps Verilog14 lessons · 2 hLearn Verilog HDL from zero. Modules, logic, flip-flops, FSMs, and testbenches, explained as simply as possible.BeginnerVerilogEDA PlaygroundIcarus Verilog

Front-end

Design and verify the RTL before it becomes gates.

Design Verification14 lessons · 2 hLearn to break designs before silicon does. Self-checking testbenches, constrained random, coverage, assertions, and UVM basics.BeginnerSystemVerilogUVMEDA Playground Clock Domain Crossing8 lessons · 68 minCross clocks safely. Metastability, synchronizers, async FIFOs, handshakes, and reset CDC, explained simply.IntermediateVerilogSystemVerilogCDC analysis Hardware Protocols8 lessons · 64 minHow blocks and chips talk. AMBA (AXI, AHB, APB) plus SPI, I2C, and UART, explained simply.IntermediateAMBAAXISPI / I2C / UART

Back-end

Turn RTL into a signoff-clean layout.

Synthesis11 lessons · 2 hTurn RTL into a gate-level netlist. Constraints, mapping, and quality of results.BeginnerDesign CompilerGenus Physical Design11 lessons · 2 hRTL to GDSII on a real flow. Floorplanning, placement, CTS, routing, and signoff.IntermediateICC2InnovusPrimeTime Static Timing Analysis16 lessons · 3 hSetup, hold, clocks, and signoff with PrimeTime. The language of timing closure.IntermediatePrimeTimeTempus Physical Verification12 lessons · 84 minDRC, LVS, and antenna checks. Prove the layout is manufacturable and matches intent.IntermediateCalibreIC Validator

Specialized

Power intent and testability across the flow.

Low Power Design & UPF13 lessons · 2 hCut dynamic and leakage power: clock gating, multi-Vt, power domains, and UPF intent.AdvancedUPFPrimePower Design for Test8 lessons · 64 minMake chips testable. Fault models, scan, ATPG, compression, MBIST, and JTAG, from scratch.IntermediateScanATPGJTAG

Tools & career

The scripting, the terminal, and the interview.

TCL for EDA7 lessons · 54 minThe scripting language behind every EDA tool. Variables, lists, procs, report parsing, and design collections.BeginnerTCLDesign CompilerPrimeTime Linux for VLSI7 lessons · 53 minEvery EDA tool runs on Linux. The shell, files, grep, pipes, ssh, and scripting, for chip engineers.BeginnerLinuxBashssh Interview Q&A5 lessons · 55 min90+ real VLSI interview questions across Synthesis, PD and STA, with a cheatsheet and glossary.All levels Career Roadmap9 lessons · 42 minPick your domain, follow a fresher-to-pro learning path, and prep with an 8-week plan.All levels