Learning Paths

Number systems, gates, Boolean algebra, K-maps, and sequential logic — the foundation under every chip.

Learn Verilog HDL from zero. Modules, logic, flip-flops, FSMs, and testbenches, explained as simply as possible.

Learn to break designs before silicon does. Self-checking testbenches, constrained random, coverage, assertions, and UVM basics.

Cross clocks safely. Metastability, synchronizers, async FIFOs, handshakes, and reset CDC, explained simply.

How blocks and chips talk. AMBA (AXI, AHB, APB) plus SPI, I2C, and UART, explained simply.

Turn RTL into a gate-level netlist. Constraints, mapping, and quality of results.

RTL to GDSII on a real flow. Floorplanning, placement, CTS, routing, and signoff.

Setup, hold, clocks, and signoff with PrimeTime. The language of timing closure.

DRC, LVS, and antenna checks. Prove the layout is manufacturable and matches intent.

Cut dynamic and leakage power: clock gating, multi-Vt, power domains, and UPF intent.

Make chips testable. Fault models, scan, ATPG, compression, MBIST, and JTAG, from scratch.

90+ real VLSI interview questions across Synthesis, PD and STA, with a cheatsheet and glossary.

Pick your domain, follow a fresher-to-pro learning path, and prep with an 8-week plan.

The scripting language behind every EDA tool. Variables, lists, procs, report parsing, and design collections.

Every EDA tool runs on Linux. The shell, files, grep, pipes, ssh, and scripting, for chip engineers.