The engineering platform for semiconductor design
Practical VLSI learning from RTL to GDSII — real workflows, tools, and interview-ready practice.
The stack
The whole chip-design stack
15 paths. One connected flow.
- 15
- paths
- 40+
- topics
- 128
- STA Q&A
The flow
From RTL to GDSII
Follow a design through the complete RTL-to-GDSII flow, from RTL through signoff.
A single design as it moves down the flow — each stage adds a layer, from behaviour to geometry.
- 01
RTL
Describe the hardware in Verilog / SystemVerilog — the behaviour, cycle by cycle.
- 02
Synthesis
Map the RTL onto real standard cells, optimized for timing, area and power.
- 03
Floorplan
Set die size and core area, place the macros, build the power grid.
- 04
Placement
Place every standard cell — balancing timing against routing congestion.
- 05
Clock Tree
Build a balanced clock tree so the clock reaches every flop with minimal skew.
- 06
Routing
Connect every net across the metal stack — DRC-correct, on-grid.
- 07
Timing Signoff
Close setup and hold across every corner and mode. Sign the timing off.
- 08
Physical Verification
DRC, LVS and antenna checks — prove the layout is actually manufacturable.
Engineering Lab
Real design. Real violations.
Real engineering.
Debug real design problems from real reports.
Setup violation
- clock arrival
- 2.000 ns
- data arrival
- 2.143 ns
- required time
- 1.890 ns
- net delay
- 0.38 ns
- transition
- 0.21 ns
- logic depth
- 18 levels
Setup · Hold · Congestion · CTS/Skew · Transition — five real problems, one bench. Full cases inside the Lab.
Knowledge → tools
Where knowledge meets the tools
Concept → Command → Report → Debug.
Concept
CPPR
Command
report_timing
Report
slack · latency · delay
Debug
shared clock over-pessimism
Solution
CPPR-aware analysis
Industry EDA tools
Knowledge hub →- Synthesis
- Design Compiler · Genus
- Physical Design
- ICC2 · Innovus · Fusion Compiler
- STA
- PrimeTime · Tempus
- Physical Verification
- Calibre · IC Validator
- Open source
- OpenROAD · OpenLane
Prove
Prove your engineering skills
Real scenarios. Real reasoning.
Your design passes timing before CTS. After CTS, WNS −87 ps. How do you debug it?
Career
From learning to a silicon role
Learn. Practice. Prove. Get hired.
- Learn
- Practice
- Prove
- Get hired
The outcome · Jobs
A VLSI job board for the skills you just built
Mentorship
Mock interviews with working engineers
Community
Engineers who ship silicon
Getting negative slack after CTS in ICC2. Already tried adjusting clock uncertainty. What else should I check?
My setup was clean before CTS but now I have negative slack on a handful of paths. I lowered clock uncertainty but it barely moved. Where do I look next before I start throwing optimization at it?
Is it worth learning Fusion Compiler if my company still uses ICC2?
We are on ICC2 and not migrating soon. Should I spend my own time learning Fusion Compiler now or wait until the team moves?
Trusted
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Go further
Structured programs, focused outcomes
Interview Bootcamp
₹499₹29990+ real interview questions with detailed answers across PD, Synthesis, STA, and PV.
OpenLane RTL-to-GDS
₹1,999₹999Full RTL to GDSII flow using OpenLane on a real design, step by step.
Get certificate. Pass the final exam, verifiable at siliconpath.in/verify
Fresher Pack
₹299₹199Complete beginner roadmap for VLSI freshers, with an 8-week structured study plan.
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Free, structured, built by engineers who ship silicon.