Learn VLSI design, from RTL to GDSII
Every stage of the flow the way it runs in industry: the commands, the reports, the fixes, and the interview questions that follow.
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The whole chip-design stack
15 paths, 154 lessons and 38 hub topics. One connected flow.
- Digital Electronics11 lessons
- Verilog14 lessons
- Design Verification14 lessons
- Clock Domain Crossing8 lessons
- Hardware Protocols8 lessons
- Synthesis11 lessons
- Physical Design11 lessons
- Static Timing Analysis16 lessons
- Physical Verification12 lessons
- Low Power Design & UPF13 lessons
- Design for Test8 lessons
- TCL for EDA7 lessons
- Linux for VLSI7 lessons
- Interview Q&A5 lessons
- Career Roadmap9 lessons
Popular courses and projects
Build a real chip, practise the interview, learn the whole flow from the book, and follow a plan to your first offer.
IntermediateSiliconPath · Project · Video
Project 1: RISC-V CPU from RTL to GDSII
Take a real RISC-V CPU from RTL to GDSII with OpenLane, one HD video episode at a time.
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Mock Interviews: Interview Ready Pack
Three one-on-one mock interviews with feedback, plus resume and LinkedIn reviews.
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IntermediateSiliconPath · Book · Read online
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BeginnerSiliconPath · Course · Self-paced
Fresher Pack
A 6-month roadmap and a 16-week study plan for VLSI freshers, with written test patterns and interview Q&A.
16-week plan₹199
From RTL to GDSII
Nine stages, from Verilog to the layout a foundry builds. Each names the industry tools and the open-source ones you can run at home.
A single design as it moves down the flow, each stage adds a layer, from behaviour to geometry.
- 01
RTL
Describe the hardware in Verilog / SystemVerilog, the behaviour, cycle by cycle, and simulate it.
- 02
Synthesis
Map the RTL onto real standard cells, optimized for timing, area and power.
- 03
Floorplan
Set the die and core size, place the macros, and build the power grid: ring, straps and rails.
- 04
Placement
Place every standard cell in the rows, balancing timing against routing congestion.
- 05
Clock Tree
Build the clock tree so the clock reaches every flop and macro with low skew and latency.
- 06
Routing
Connect every net across the metal stack, DRC-correct, on-grid.
- 07
Timing Signoff
Extract the wire parasitics, then close setup and hold across every corner and mode. Sign the timing off.
- 08
Physical Verification
DRC and antenna checks prove the layout can be manufactured; LVS proves it matches the netlist.
- 09
GDSII
Stream out the final layout and tape out: the file the foundry turns into silicon.
Engineering Lab: the violations you will debug on the job
Worked examples in the shape of real signoff reports. Read the numbers, find the cause, choose the fix.
Setup violation
- clock period
- 2.000 ns
- uncertainty
- 0.050 ns
- setup time
- 0.060 ns
- required time
- 1.890 ns
- data arrival
- 2.033 ns
- logic depth
- 18 levels
Setup · Hold · Congestion · CTS/Skew · Transition: five classic signoff problems, one bench. Full cases inside the Lab.
Read a real timing report, line by line
One setup path that fails only because the clock is counted twice: the concept, the command, the report and the fix.
Worked example in PrimeTime's report format. The numbers are chosen to teach, and every line adds up.
- 1
Concept
On-chip variation. Derates make the launch clock late and the capture clock early, so the check is pessimistic by design.
set_timing_derate -late 1.06 set_timing_derate -early 0.95
- 2
Command
Ask the tool for the worst setup path.
report_timing -delay_type max
- 3
Report
Slack is -0.085 ns. The path fails, but only just.
- 4
Debug
Both clocks run through the same 1.018 ns of buffers before they split. That shared stretch is counted late for launch and early for capture at once, which cannot happen in silicon: 1.018 × 0.11 = 0.112 ns of false pessimism.
- 5
Solution
Remove it. The report gains a CRPR line and the path passes with +0.027 ns.
set timing_remove_clock_reconvergence_pessimism true
Tools covered in the lessons
Knowledge hub- Synthesis
- Design Compiler · Genus
- Physical Design
- ICC2 · Innovus · Fusion Compiler
- STA
- PrimeTime · Tempus
- Physical Verification
- Calibre · IC Validator
- Open source
- Yosys · OpenROAD · OpenSTA · Magic · KLayout
Get interview-ready, then get hired
Practise the way interviews are run, show proof anyone can check, then apply.
Your design passes timing before CTS. After CTS, WNS -87 ps. How do you debug it?
A strong answer covers
- 1Compare the path before and after CTS: ideal clocks are now real, so skew and latency have changed.
- 2Check whether the launch clock got later or the capture clock got earlier, and by how much.
- 3Fix the skew in the clock tree or speed up the data path, then re-run timing on every corner.
Questions from the community
Start with the free lessons
154 lessons across 15 paths, written by engineers who ship silicon.