PV Tool Knowledge
Calibre from Siemens and IC Validator from Synopsys: what each signoff verification tool does and how they compare.
Three commercial tools dominate signoff physical verification: Calibre from Siemens EDA, IC Validator from Synopsys and Pegasus from Cadence. They do the same jobs (DRC, LVS, fill, ERC and more) and each is certified by the major foundries, which supply rule decks written in the tool's own language. This lesson covers how each is used and what an engineer is expected to know about them.
Calibre (Siemens EDA)
Calibre has been the reference signoff tool for decades, and almost every foundry ships Calibre decks first. Its rules are written in SVRF (Standard Verification Rule Format), often with Tcl-based TVF for generated rules. In batch mode, the rule file is the command's argument, and the layout path, top cell and output files are set inside that file.
| Job | Typical command | Notes |
|---|---|---|
| DRC | calibre -drc -hier -turbo 16 drc_run.svrf | Hierarchical, multithreaded |
| LVS | calibre -lvs -hier -turbo 16 lvs_run.svrf | Source netlist in SPICE; convert Verilog with v2lvs |
| Fill | calibre -drc -hier fill_run.svrf | The foundry fill deck is run as a DRC job that generates shapes |
| Parasitic extraction | Calibre xACT or xRC | Produces SPEF for signoff STA |
| ERC / PERC | Rules in the LVS or a PERC deck | Voltage-aware and ESD checks |
| Results review | calibre -rve chip_top.drc.results | RVE highlights errors in the layout viewer |
IC Validator (Synopsys)
IC Validator (ICV) is tightly integrated with Synopsys implementation tools. From ICC2 or Fusion Compiler, commands such as signoff_check_drc and signoff_create_metal_fill run ICV on the live design, so engineers can find and fix signoff DRC before streaming out. ICV runsets are written in PXL. A standalone run names the layout, the top cell and the runset.
# Standalone
icv -i chip_final.gds -c chip_top -f GDSII drc_runset.rs
# From inside ICC2
signoff_check_drc
signoff_fix_drc ;# automatic repair of common violationsPegasus (Cadence)
Pegasus is Cadence's signoff verification tool, integrated with Innovus for digital and Virtuoso for custom layout. Like ICV in ICC2, it can run in-design from Innovus so DRC and fill are checked on the real implementation. It is built for massively parallel runs across many machines.
Open-source tools
- Magic: layout editor and DRC engine, used for Sky130 and GF180 open PDKs.
- KLayout: fast layout viewer with DRC and LVS scripting in Ruby or Python.
- Netgen: LVS comparison, used in OpenLane.
Comparison
| Calibre | IC Validator | Pegasus | |
|---|---|---|---|
| Vendor | Siemens EDA | Synopsys | Cadence |
| Rule language | SVRF / TVF | PXL | Its own format; many foundries supply native decks |
| In-design use | From ICC2 and Innovus via integrations | Native in ICC2 and Fusion Compiler | Native in Innovus and Virtuoso |
| Foundry support | Universal, usually first | Major foundries | Major foundries |
| Results viewer | RVE | VUE | Integrated in Innovus and Virtuoso |
Interviewers rarely test exact tool syntax. They test whether you understand the flow: signoff runs on merged GDS, decks come from the foundry and must not be edited, LVS needs a SPICE source netlist, and in-design checks are an early filter, not a replacement for signoff.
Only a deck certified for your exact process and version counts for signoff. Running an older deck, or a different tool's deck than the one the foundry certified for your tape-out, can hide real violations. Check the deck version against the foundry's release notes before the final run.
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