PV Flow Overview

Physical verification (PV) is the set of checks that prove a finished layout can be manufactured and is the circuit you meant to build. It runs on the final layout database, after place and route, and it is the last engineering gate before the design goes to the foundry. This lesson walks through the whole flow: what goes in, which checks run, in what order, and how failures get fixed.

The inputs

Why the layout has to be merged first

Place and route tools do not work with full cell layouts. They use abstracts (LEF views) that show only a cell's outline, pins and routing blockages. The real transistors and internal wiring live in the cells' own GDS files. Before PV, the routed design is streamed out and merged with the GDS of every standard cell, memory and IP block, so the checker sees every shape. Many first-run PV errors are really merge errors: a missing cell GDS, a name mismatch between LEF and GDS, or a wrong layer map.

The checks, in order

1. DRC (design rule check): every shape obeys the foundry's width, spacing, enclosure and area rules. Most decks include the antenna rules too, or ship them as a separate deck.
2. LVS (layout versus schematic): the circuit extracted from the layout matches the source netlist, device for device and net for net.
3. ERC and PERC (electrical rule checks): no floating gates, correct well connections, latchup and ESD rules met, no thin-oxide devices on high voltages.
4. Fill and density: dummy metal and other fill is inserted, then density rules are checked.
5. Final DRC and LVS on the filled layout, because fill can create new spacing violations and, if it touches a net, new shorts.

In practice these run in parallel on a compute farm and iterate many times in the last weeks before tape-out. The order matters for debugging: a short that LVS reports is often easier to find once DRC is clean.

In-design checks versus signoff

Routers check design rules as they route, and tools can call the signoff checker from inside the implementation database (IC Validator from ICC2, Pegasus from Innovus, or Calibre in either). This catches most problems early. Signoff PV still runs on the fully merged GDS, because only there does the checker see the insides of cells, the interaction between neighbouring cells and the final fill.

Fixing and closing

• Fix in the implementation database, not in the GDS. Editing GDS directly breaks the link to the netlist and your fix vanishes on the next stream-out. Late GDS edits are sometimes allowed but must be tracked carefully.
• Triage by rule: sort violations by rule and count, fix the biggest groups with scripts or ECO commands, then re-run.
• Waivers: a few violations may be accepted with the foundry's written approval, typically inside foundry-certified IP. Never waive something you do not understand.
• Tape-out is allowed only when every deck is clean or formally waived on the final, filled GDS.

The tools