LVS: Layout vs. Schematic

Layout versus schematic (LVS) proves that the layout implements the intended circuit. The tool extracts a netlist from the layout, finding every transistor from the overlap of poly and diffusion and tracing every connection through metal and vias, and then compares it with the source netlist. If a wire is broken, two nets touch, or a device is missing, LVS finds it.

How LVS works

1. Extraction: the tool recognises devices from layer combinations (a poly shape crossing diffusion forms a transistor) and measures their parameters, such as width and length.
2. Connectivity: it follows metal, vias and contacts to build the layout's nets. Text labels on pins give nets their names.
3. Comparison: it matches the extracted netlist to the source, starting from named ports and power nets and working inward, device by device and net by net.

The source netlist for a digital block is the final netlist written by the place and route tool, not the synthesis netlist, because place and route adds buffers, clock tree cells, tie cells and ECO changes. LVS tools compare transistor-level netlists, so the Verilog netlist is converted to SPICE (Calibre uses the v2lvs utility for this) and linked with the standard cells' own transistor netlists (CDL files).

# 1. Convert the PnR Verilog netlist to a SPICE netlist for LVS
v2lvs -v chip_top_pnr.v -o chip_top.sp -s std_cells.cdl

# 2. A small wrapper around the foundry LVS deck
#    LAYOUT PATH     "chip_final.gds"     LAYOUT PRIMARY  "chip_top"
#    SOURCE PATH     "chip_top.sp"        SOURCE PRIMARY  "chip_top"
#    LVS REPORT      "chip_top.lvs.report"
#    INCLUDE "/pdk/calibre/lvs/foundry_lvs.svrf"
calibre -lvs -hier -turbo 16 lvs_run.svrf

# 3. The report ends with CORRECT or INCORRECT
grep -E "CORRECT|INCORRECT" chip_top.lvs.report

The errors you will see

Digital-flow causes that catch people out

• Physical-only cells: fillers, decaps, well taps and end caps exist in the layout but not in a logical netlist. Export the netlist with these cells and with power and ground connections, or the comparison will be missing them.
• Power connections: every cell's supply pins, and the wells and substrate, must connect to the right supply. A missing via in the power grid leaves a row's well floating and shows up as an open on VDD or VSS.
• Macros: a memory or IP block needs its own LVS netlist, or it must be treated as a black box on both sides with matching pins.
• Labels: top-level pin labels must be on the correct text layer and match the netlist port names exactly, including case.

Worked example: VDD shorted to VSS

The report says INCORRECT, with a single line that matters most: the nets VDD and VSS are merged in the layout. A power-to-ground short is the most serious LVS failure, because the chip would draw huge current on power-up.

1. Short isolation: Calibre RVE, and similar tools in ICV and Pegasus, can trace the shortest path of shapes that joins the two nets. Run it rather than searching by eye.
2. The path goes through a Via3 where a VSS strap crosses a VDD strap. The power grid script dropped a via at every strap intersection, regardless of net.
3. Fix the script so vias are only placed where the two straps belong to the same net, rebuild the grid, re-route the affected area, stream out and re-run LVS.

Note the order: always clear shorts before chasing other mismatches. One short merges two big nets, and the comparison then reports hundreds of confusing follow-on errors that disappear once the short is fixed.