Antenna Check
Why metal connected to a gate collects charge during plasma etching, how the antenna ratio is checked, and how violations are fixed.
The antenna effect is damage done to transistors while the chip is being made, not while it runs. During plasma etching, exposed metal collects electric charge. If a piece of metal is connected to a transistor gate and to nothing else yet, that charge has only one way out: through the gate's very thin oxide. Enough charge will damage the oxide, shifting the transistor's threshold voltage or destroying it outright.
Why the order of manufacturing matters
A chip is built from the bottom up: transistors first, then Metal1, then Via1 and Metal2, and so on. While Metal1 is being etched, only the Metal1 shapes exist, so a gate "sees" only the Metal1 connected to it at that moment. Higher layers do not exist yet. Only when the full net is built up to its highest layer does it also connect to the driving cell's output, whose diffusion forms a diode that safely drains any charge.
So what matters is how much metal is connected to a gate, on each layer, before the net reaches a diffusion. That is exactly what the antenna rule measures.
The antenna ratio
Antenna ratio (for a layer) =
area of metal on that layer connected to the gate
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area of the gate oxide it connects to
Some PDKs use the metal's side-wall area (perimeter × thickness)
instead of top area, and many also check a cumulative ratio
that adds the lower layers. The exact rules come from the PDK.Worked example
A driver on one side of a block feeds a single gate 400 µm away over a Metal1 wire. The numbers below are illustrative.
Gate area = 0.05 µm²
Metal1 wire: 0.1 µm × 400 µm = 40 µm²
Metal1 antenna ratio = 40 / 0.05 = 800
PDK limit for Metal1 = 400 → violation
Fix: route 100 µm on Metal1 near the gate, then jump up to Metal3
for the long run and come back down at the driver.
Metal1 connected to the gate = 0.1 × 100 = 10 µm²
Metal1 antenna ratio = 10 / 0.05 = 200 → passes
When Metal3 is etched, the net already reaches the driver's
diffusion through the lower layers, so the charge drains safely.The three fixes
| Fix | How it works | Cost |
|---|---|---|
| Layer jumping | Break the long run on a low layer and bridge it on a higher layer near the gate, so little metal touches the gate before the net is complete | An extra via pair and a little routing; the preferred fix |
| Antenna diode | Add a reverse-biased diode from the net to ground next to the gate. During manufacturing it leaks the charge away before it can damage the oxide | A small extra capacitance and leakage on the net |
| Buffer insertion | Split the long net with a buffer near the gate, so the gate's net is short | Area and delay; usually only if timing wants the buffer anyway |
Routers fix most antenna violations automatically when the antenna rules and the cells' antenna data are loaded. Standard cell LEF files carry gate and diffusion area for each pin (ANTENNAGATEAREA and ANTENNADIFFAREA), which is how the router knows what each wire is connected to.
# OpenROAD / OpenLane
check_antennas
repair_antennas ;# inserts diodes where jumping is not enough
# Innovus
setNanoRouteMode -drouteFixAntenna true
verifyProcessAntenna -report antenna.rptThe key insight to give in an interview: antenna damage happens during fabrication, layer by layer, which is why jumping to a higher layer works. The gate is protected because the net reaches a diffusion before the long wire is connected to the gate.
Antenna diodes add capacitance and leakage, and a clock net with many diodes gets slower. Prefer layer jumping on timing-critical and clock nets, and review diode counts after routing.
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