Metal Fill & Density Rules
Why chemical mechanical polishing needs uniform metal density, how density rules are checked, and how metal fill fixes them.
Each metal layer of a chip is polished flat by chemical mechanical polishing (CMP) before the next layer is built. CMP removes material at a rate that depends on how much metal is in the area: sparse regions polish differently from dense ones. If density varies too much, the surface ends up uneven, wires come out thinner or thicker than designed, and vias on the next layer may miss. Density rules keep every region of every layer within a band, and metal fill is how designs meet them.
What goes wrong without fill
- Dishing: in wide or isolated copper areas the polish scoops metal out of the middle, thinning the wire and raising its resistance.
- Erosion: in very dense areas the insulator between wires is polished away too, thinning everything in the region.
- Topography: an uneven surface throws the next layer's lithography out of focus, which causes shorts and opens higher up the stack.
Density rules
| Rule | Typical form | Why |
|---|---|---|
| Minimum density | Metal must cover at least a set share of each check window, often around 20 to 30% | Sparse areas dish and polish unevenly |
| Maximum density | Metal must not exceed a set share, often around 70 to 80% | Very dense areas erode |
| Check window | A square window, from tens to a few hundred microns on a side, stepped across the die | Density is judged locally, not as a chip average |
| Gradient | Density may not change too much between neighbouring windows | Sharp changes create steps in the polished surface |
| Fill geometry | Fill shapes have their own width, spacing and fill-to-signal spacing rules | Fill must be manufacturable and keep away from real wires |
The exact numbers are set per layer in the foundry's rule deck, and they differ between processes. Treat the values above as the shape of the rules, not as limits for your design.
Many PDKs also have a gradient rule that limits how much density can change between neighbouring windows, and density rules for front-end layers such as poly and diffusion, which standard cell fillers and dedicated fill cells take care of.
Worked example: filling a sparse window
Check window = 50 µm × 50 µm = 2,500 µm²
Metal2 area in the window = 400 µm²
Density = 400 / 2,500 = 16%
Rule: minimum 20%, target 25%
Metal needed at 25% = 0.25 × 2,500 = 625 µm²
Fill to add = 625 − 400 = 225 µm²
With 0.5 µm × 5 µm fill shapes (2.5 µm² each) → 90 shapes,
placed at least the fill-to-signal spacing away from real wires.Fill and timing
Fill is extra metal, so it adds coupling capacitance to nearby signal wires. Floating fill couples to every wire around it, and grounded fill behaves like a shield with a fixed capacitance to ground. Either way, timing after fill differs from timing before it.
- Timing-driven fill keeps a larger spacing from critical nets and clock nets.
- Signoff parasitic extraction and STA are run on the filled layout, or with a fill-aware extraction model, so the final timing includes the fill.
- Fill shapes must not connect to signal nets; a fill shape touching two nets creates a short that LVS will catch.
When and how fill is inserted
Fill goes in after routing is complete and before final signoff. It is usually generated by the foundry's fill deck in the signoff tool, or by in-design fill that calls that tool from the implementation database, for example signoff_create_metal_fill in ICC2. Afterwards, DRC and LVS are run again on the filled GDS.
# Calibre: run the foundry fill deck, which writes the fill shapes
# to a separate GDS that is merged with the design for signoff
calibre -drc -hier -turbo 16 fill_run.svrf
# ICC2: in-design fill, timing-aware, using IC Validator underneath
signoff_create_metal_fill -timing_preserve_setup_slack_threshold 0.05In an interview, connect fill to three things: CMP needs uniform density, fill adds capacitance so signoff timing must include it, and fill must never touch a signal net. That shows you understand fill as a manufacturing, timing and verification topic at once.
Leaving fill to the very end is risky on dense designs. If a region is already above the maximum density, fill cannot help; the routing itself has to spread out. Check density early, after the first full route.
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