ERC: Electrical Rule Check
ERC catches electrical issues that DRC and LVS miss. A layout can be DRC-clean and LVS-clean but still have electrical errors that cause chip malfunction.
A layout can pass DRC and LVS and still fail electrically. DRC checks shapes and LVS checks connectivity against the netlist, but neither asks whether the circuit is electrically safe: whether a gate is left floating, whether wells are biased, whether a thin-oxide transistor sits on a high-voltage net, or whether a pad can survive an electrostatic discharge. Electrical rule checks (ERC) and their programmable extension, PERC, answer those questions.
What ERC checks
| ERC Check | What It Detects | Consequence if Missed |
|---|---|---|
| Floating Gate | MOSFET gate connected to nothing (floating net) | Gate floats to indeterminate voltage → random switching behavior. Very common ERC error in early PD. |
| Floating Well | N-well or P-well not connected to VDD/VSS | Well floats → transistors biased incorrectly → latchup risk, parametric failures |
| VDD/VSS Short | Power and ground nets connected together | Direct short circuit → chip draws excessive current → burns out immediately on power-up |
| Input Not Driven | Logic input pin with no driver | Input floats → oscillation, metastability, excessive power consumption |
| Output Contention | Two outputs driving the same net simultaneously | Short circuit between drivers → device damage, incorrect logic level |
| ESD Violation | I/O pad has insufficient ESD protection structure | ESD event during handling destroys input gate oxide → dead chip before it even runs |
| Latchup Violation | Tap cells too far from active region (>50µm) | Parasitic SCR triggers → VDD-to-VSS latchup → chip permanently damaged |
Latchup and well taps
In bulk CMOS, every inverter contains a parasitic thyristor: a PNP transistor formed by the PMOS source, the N-well and the P-substrate, and an NPN formed by the NMOS source, the substrate and the N-well. If a disturbance turns both on, they latch each other on and short VDD to VSS until power is removed. This is latchup.
Well taps prevent it. They tie the N-wells to VDD and the substrate to VSS at regular intervals, keeping the well resistance low so the parasitic transistors never get enough base voltage to turn on. In a standard cell design, tap cells are placed in every row at a fixed pitch, and the latchup rule sets a maximum distance from any transistor to its nearest tap. The PDK and library define that distance; on many processes it is a few tens of microns.
PERC: voltage-aware and ESD checks
PERC (programmable electrical rule checking) runs rules that need to understand the circuit, not just the shapes. Two uses dominate in digital chips.
- Voltage-aware checks: with multiple supply voltages, PERC propagates voltages through the netlist and flags thin-oxide gates driven from a higher-voltage domain, or crossings with no level shifter.
- ESD checks: every I/O pad must have a protection path to the supplies, with wide enough metal and low enough resistance to carry an ESD discharge. PERC measures the resistance of those paths and checks the protection devices exist.
Worked example: a floating input
ERC reports a floating gate on an input pin of a spare NAND2 cell in a quiet corner of the block. Spare cells are placed so that post-mask ECOs can use them, and their inputs must be tied to a fixed level until then.
- Check the netlist: the spare cell's inputs are meant to connect to a tie-low cell.
- Check the layout: the tie cell exists, but its output was never routed because the net was marked "don't route" during an earlier ECO experiment.
- Fix: remove the attribute, route the tie net, re-run LVS and ERC.
A floating gate is dangerous even in an unused cell. It drifts to a mid-rail voltage, turning on both transistors of its input stage and drawing a steady short-circuit current, and it can pick up charge that damages the oxide.
A useful way to explain the three checks: DRC asks "can it be built?", LVS asks "is it the right circuit?", and ERC asks "is the circuit electrically safe?". Latchup, floating gates and ESD protection are the three ERC topics interviewers ask about most.
Tap cells are physical-only cells with no logic function, so nothing in timing or simulation will complain if a region is missing them. Only the latchup rule check catches it. After any floorplan change that adds or moves blockages, re-check tap coverage.
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