DRC: Design Rule Check
How DRC checks layout geometry against the foundry rules for width, spacing and enclosure, and why those rules exist.
Design rule checking (DRC) verifies that every shape in the layout can actually be manufactured. A lithography system cannot print a wire narrower than some minimum, an etch cannot separate two shapes closer than some minimum, and a via that is not fully covered by metal may fail to connect. The foundry turns these limits into thousands of geometric rules, and DRC checks every polygon against them.
The rule families
| Rule Category | What It Checks | Why It Exists | Typical Fix |
|---|---|---|---|
| Minimum Width | Wire width ≥ Wmin per metal layer | Too-thin wires break during CMP or have excessive resistance / EM risk | Widen the wire; router usually handles this automatically |
| Minimum Spacing | Gap between same-layer shapes ≥ Smin | Lithography cannot resolve too-small gaps → shorts between wires | Increase routing track separation; re-route in congested area |
| Via Enclosure | Metal must extend beyond via edge by min amount on all sides | Overlay (misalignment) in fab could expose via without metal contact | Use larger via enclosure design rule; ensure auto-router uses correct rules |
| Via Coverage | Minimum number of vias on high-current nets | Single via has limited current capacity; EM requires multiple vias | Replace single-cut vias with via arrays; use via doubling ECO |
| Notch Rule | Internal notch (concave corner) ≥ Nmin | Narrow notches print incorrectly - corners round off → shape deformation | Fill small notches; ensure polygon merging after fill insertion |
| Area Rule | Minimum enclosed polygon area | Tiny isolated shapes may not print or etch completely | Remove floating metal shapes; merge small disconnected polygons |
| Extension Rule | Active/poly must extend beyond diffusion edge | Transistor channel defined by overlap; insufficient extension = no transistor | Standard cell library handles this; flagged in custom analog layout |
| Density Rules | Min/max metal fill % per window per layer | CMP planarization requires uniform metal density across the wafer | Run fill insertion tool (Calibre Fill); remove excess fill if over-dense |
| Double-Patterning | Adjacent same-mask shapes must be separable into 2 colors | At <20nm, single lithography cannot print minimum pitch → 2 exposures needed | Assign colors using DP-aware router; fix coloring conflicts |
| Poly Spacing to Diff | Minimum distance between poly gate and nearby diffusion | Gate coupling to adjacent diffusion can cause leakage or latchup | Handled by standard cell design; appears in custom layout |
Beyond these basics, advanced nodes add rules that depend on context: spacing that grows with wire width (wide-metal rules), end-of-line spacing where a wire ends facing another, minimum step and jog sizes, via-to-via spacing, and coloring rules for multi-patterned layers. The rule count grows from a few hundred at mature nodes to many thousands below 10 nm.
Reading rule names
Each rule has an ID in the foundry's design rule manual, usually built from the layer, the kind of check and a number. For example, M2.S.1 might be "minimum spacing of Metal2" and M2.W.1 "minimum width of Metal2". Knowing the naming scheme lets you read a violation report at a glance and look up the exact definition when a result is surprising.
Running DRC with Calibre
In batch mode, Calibre takes the rule file as its argument. The layout file, top cell and output locations are set inside that file, usually in a small wrapper that includes the foundry deck.
# drc_run.svrf: a small wrapper around the foundry deck
LAYOUT PATH "chip_final.gds"
LAYOUT PRIMARY "chip_top"
LAYOUT SYSTEM GDSII
DRC RESULTS DATABASE "chip_top.drc.results" ASCII
DRC SUMMARY REPORT "chip_top.drc.summary"
INCLUDE "/pdk/calibre/drc/foundry_drc.svrf"
# Run hierarchically on 16 threads
calibre -drc -hier -turbo 16 drc_run.svrf
# Review results graphically
calibre -rve chip_top.drc.resultsWorked example: triaging a DRC run
A first full-chip run reports 1,240 violations. The summary, sorted by count, looks like this (illustrative):
RULE COUNT MEANING
M3.S.2 812 Metal3 spacing, wide wire (> 0.2 µm) to neighbour
V2.EN.1 301 Metal2 enclosure of Via2
M1.A.1 96 Metal1 minimum area
PO.S.4 31 poly spacing at a macro boundary- Start with the biggest group. 812 M3 wide-spacing errors in one region of the chip usually share one cause. Here they sit along one edge of a memory macro, where the power straps are wider than the router expected. The fix is in the power grid script, not wire by wire.
- The 301 Via2 enclosure errors appear only at the boundary of a hard IP block. The block's abstract did not show a Metal2 blockage, so the router placed vias too close to the IP's internal metal. Fix the abstract (LEF) and re-route that area.
- The 96 minimum-area errors are tiny Metal1 stubs left by the router at pin access points. Most routers have an option to fix minimum area automatically; enable it and run an ECO route.
- The 31 poly errors are inside the macro itself. Check whether the IP vendor or foundry already waived them before touching anything.
The pattern is typical: a few root causes produce almost all the violations, and they are fixed upstream, in scripts, abstracts or router settings. Fixing shapes one at a time is a last resort.
Don't try to fix DRC violations randomly. Sort by rule, then by count; the top few rules usually account for most violations. Fix one rule family at a time, re-run, and watch for side effects: fixing a spacing error can create a new width or area error nearby.
A clean in-design check inside the router does not mean a clean signoff DRC. The router sees only cell abstracts, so violations between a wire and a cell's internal metal, or between two neighbouring cells, appear only when the merged GDS is checked.
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