VLSI Domains: Which One Is for You?

Most digital VLSI jobs fall into six domains. They differ in what you do all day, which tools you live in, and what interviews test. This lesson describes each one concretely so you can pick a first target. The work style matters as much as the topic: some people love writing code, others love chasing a timing report down to the last picosecond.

RTL design engineer

You turn a specification into hardware: microarchitecture, then synthesizable Verilog or SystemVerilog for state machines, pipelines, datapaths and interfaces. You work closely with architects above you and with verification and synthesis beside you, and you fix the bugs they find.

• Day to day: writing and reviewing RTL, lint and CDC checks, debugging failing tests, estimating area and timing with synthesis.
• Skills: Verilog and SystemVerilog, digital logic, computer architecture, clocking and resets, CDC.
• Start with: Digital Electronics, Verilog, Clock Domain Crossing.

Design verification (DV) engineer

You prove the RTL works before it becomes silicon. DV is the largest front-end job category, because verification usually takes more effort than design. You build testbenches, write constrained-random tests, assertions and coverage models, and debug failures down to the line of RTL.

• Day to day: writing UVM components and sequences, running regressions, closing coverage holes, debugging waveforms.
• Skills: SystemVerilog, UVM, SVA, functional coverage, a scripting language, and enough protocol knowledge to model real interfaces.
• Start with: Design Verification and Hardware Protocols, or the DV role track.

Synthesis and DFT engineer

Synthesis engineers turn RTL into a gate-level netlist that meets timing, area and power targets, and own the constraints (SDC) that describe the design's timing. DFT engineers insert scan chains, compression and memory self-test so every manufactured chip can be tested. The two roles often sit in the same team.

• Day to day: running Design Compiler, Fusion Compiler or Genus, reviewing QoR, writing SDC, inserting and verifying scan, running ATPG.
• Skills: SDC and STA basics, Tcl, logic optimisation, scan and ATPG for DFT.
• Start with: Synthesis and Design for Test.

Physical design (PD) engineer

You turn the netlist into a layout: floorplan, power grid, placement, clock tree, routing, then timing and congestion closure until the block is clean. PD is the largest back-end job category, and it rewards people who like debugging big, messy optimisation problems.

• Day to day: running Innovus or ICC2 and Fusion Compiler, reading timing and congestion reports, adjusting floorplans, running ECOs.
• Skills: the full PD flow, STA, Tcl, Linux, and a feel for the trade-offs between timing, congestion and power.
• Start with: the PD role track.

STA engineer

You decide whether the chip is fast enough to ship. STA engineers own the constraints and the signoff timing across every mode and corner, analyse failures, and drive the ECOs that close them. Most PD engineers do a lot of STA; dedicated STA roles are common in larger teams.

• Day to day: running PrimeTime or Tempus, reviewing constraints, analysing reports, generating and checking ECOs.
• Skills: timing theory in depth (OCV, CRPR, MMMC, SI), SDC, Tcl.
• Start with: the STA role track and the 128 STA interview questions.

Physical verification engineer

You make sure the final layout can be manufactured and matches the netlist: DRC, LVS, antenna, ERC and fill, often at full-chip level where everything is merged together. It is detail work with a hard deadline, since nothing tapes out until PV is clean.

• Day to day: running Calibre, IC Validator or Pegasus, debugging shorts and opens, working with PD and IP teams on fixes.
• Skills: layout and process basics, DRC and LVS debugging, rule deck reading, scripting.
• Start with: Physical Verification.

Choosing