Essential Books, Courses & Resources
The foundational books, online resources, courses and projects worth your time.
There is far more material on VLSI than anyone can read. This list is deliberately short: the books working engineers actually keep on their desks, the free resources worth your time, and the hands-on routes that turn reading into skill.
Books
| Book | Authors | Read it for |
|---|---|---|
| Digital Design and Computer Architecture | Harris and Harris | The clearest start on digital logic and a simple processor, with Verilog |
| CMOS VLSI Design: A Circuits and Systems Perspective | Weste and Harris | The standard reference on transistors, delay, power and layout |
| Digital Integrated Circuits: A Design Perspective | Rabaey, Chandrakasan and Nikolić | Circuit-level depth on gates, interconnect and timing |
| Computer Organization and Design (RISC-V edition) | Patterson and Hennessy | Processor and memory architecture |
| Static Timing Analysis for Nanometer Designs | Bhasker and Chadha | The practical STA reference: constraints, corners, OCV, reports |
| Advanced ASIC Chip Synthesis | Bhatnagar | Synthesis with Design Compiler and the constraints behind it |
| VLSI Physical Design: From Graph Partitioning to Timing Closure | Kahng, Lienig, Markov and Hu | The algorithms inside placement, routing and timing closure |
| SystemVerilog for Verification | Spear and Tumbush | The standard entry point to SystemVerilog testbenches |
| Low Power Methodology Manual | Keating, Flynn, Aitken, Gibbons and Shi | Clock gating, power gating, retention and multi-voltage design in practice |
For physical design specifically, our own book, VLSI Physical Design, covers the algorithms, the methodology and the full RTL-to-GDSII flow with worked examples.
Free papers and standards
- Clifford Cummings' papers (Sunburst Design) on non-blocking assignments, clock domain crossing and asynchronous FIFOs. Short, practical and still the reference on these topics.
- IEEE 1800 (SystemVerilog), available at no cost through the IEEE GET program. Use it to settle questions the textbooks leave vague.
- Tool documentation for the open-source flow: the OpenROAD and LibreLane documentation explain each step and its settings.
Hands-on routes
- Open PDKs: Sky130 and GF180MCU are free, real process kits. LibreLane runs the whole flow on them.
- Tiny Tapeout: a low-cost shared shuttle that lets individuals put a small design on real silicon. Check tinytapeout.com for the current shuttle schedule.
- A RISC-V core: build a small one in Verilog, verify it, and take it through synthesis and place and route. Our OpenLane course does this with the open-source PicoRV32 core.
- Open-source contributions: fixes and documentation for OpenROAD, Yosys or cocotb are visible, verifiable work.
On this site
- Free learning paths from digital electronics to physical verification.
- 128 STA interview questions with worked answers.
- Engineering Lab: real failure cases to diagnose.
- Role tracks that order everything for one job.
Read with a pencil. After each chapter, write one worked example of your own: a timing calculation, a small circuit, a script. The act of producing an example is what turns a book into a skill.
Finished reading?
Mark it complete to track your progress through the path.
Go further
Get the full 6-month fresher roadmap, the tool order and a 16-week study plan.
Get new lessons by email
New lessons, interview prep and real EDA tool workflows. No spam.