Learning Roadmap: Fresher to Professional

This roadmap lays out what to learn at each stage of a VLSI career, from a student with no background to an engineer who owns signoff for a block. The months are a guide for someone studying steadily alongside college or work; the order matters more than the timing.

Stage 1: Foundations (about 0 to 6 months)

Everything later rests on digital logic and on being comfortable at a Linux command line. Skip this stage and every later topic feels like memorisation.

• Digital electronics: gates, flip-flops, setup and hold, state machines, number systems. Digital Electronics path.
• Verilog: synthesizable RTL, blocking versus non-blocking, testbenches. Verilog path.
• CMOS basics: how a transistor switches, why delay depends on load, where power goes.
• Linux and Tcl: files, grep, scripting, reading reports. Linux and Tcl.

Proof of this stage: a few small designs (a counter, a UART, a FIFO) written in Verilog and verified with a self-checking testbench in a free simulator.

Stage 2: Core domain (about 6 to 18 months)

Now pick a domain and go deep. For back-end, that means the flow from RTL to GDSII; for front-end, verification methodology.

• Back-end: Synthesis, Static Timing Analysis, Physical Design, Physical Verification.
• Front-end: Design Verification, Hardware Protocols, Clock Domain Crossing.
• For both: run real tools. OpenLane and Sky130 for back-end; a simulator with UVM for front-end.

Proof of this stage: one project you can defend line by line. For back-end, a design taken from RTL to a clean GDSII with timing, DRC and LVS reports you can explain. For front-end, a UVM testbench with constrained-random tests, a scoreboard and coverage for a real protocol block.

Stage 3: Professional (about years 1 to 3)

The first job teaches what no course can: production flows, real constraints, deadlines and signoff. The goal is to become the person who can close a block on your own.

• Multi-mode multi-corner timing, OCV and ECO flows.
• Low power: clock gating, multi-Vt, power domains and UPF. Low Power path.
• Debugging instinct: finding the root cause of a failure instead of trying random fixes.
• Scripting that saves your team time, not just your own.

Stage 4: Expert (about year 3 onwards)

Seniority is less about knowing more commands and more about owning outcomes: defining a block's methodology, predicting problems before they appear, and helping others close. Common directions are technical leadership of a subsystem, methodology and flow ownership, advanced-node specialisation, or moving across the boundary into architecture or EDA tool development.

How to prove each stage