Lesson 9 of 92 minAll levels
Skills Proficiency Matrix
Rate yourself against a skills matrix, and know the level to reach in your domain before your first interview.
Rate yourself honestly against this matrix. Target "Intermediate" in your primary domain and "Awareness" in adjacent domains before your first interview. "Advanced" in your domain is the 3-5 year mark.
| Skill Area | Awareness | Intermediate (Hire-ready) | Advanced (3-5yr) |
|---|---|---|---|
| Verilog / SV | Can read RTL code. Knows gates, FFs, always blocks. | Writes synthesizable RTL. Understands latch vs FF inference. Codes FSMs correctly. | Writes parameterized, reusable RTL. Knows synthesis implications of every construct. |
| Synthesis / SDC | Knows flow: RTL → netlist. Knows create_clock exists. | Writes complete SDC. Runs DC. Interprets QoR. Understands WNS/TNS. | Tunes compile strategies. Multi-Vt optimization. compile_ultra deep settings. |
| STA | Can define setup/hold time. Knows slack formula. | Reads PT timing reports. Understands MMMC. Knows OCV derating. Can close timing with ECO. | POCV, CRPR, PBA vs GBA. Develops full MMMC corner methodology for a project. |
| Physical Design | Knows PD flow stages. Can explain utilization and skew. | Can floorplan a block. Runs Innovus/OpenROAD full flow. Understands DRC and IR drop. | Closes timing at advanced nodes. Owns CTS strategy. Designs power grid from scratch. |
| Physical Verification | Knows DRC/LVS purpose. Can identify a spacing violation. | Runs Calibre DRC/LVS. Debugs top violation types. Understands antenna and fill. | Owns tape-out PV sign-off. Writes Calibre runset modifications. DP-aware verification. |
| TCL Scripting | Can read/modify existing TCL scripts. Knows variables, loops, procs. | Writes TCL flow scripts from scratch. Parses timing reports. Automates batch jobs. | Writes complex flow automation, QoR parsers, automatic ECO generators in TCL/Python. |
| Low Power | Knows clock gating saves power. Knows LVT has more leakage. | Sets up multi-Vt optimization in synthesis. Understands UPF domains and level shifters. | Designs full multi-voltage UPF architecture. Owns power sign-off (Voltus/RedHawk). |
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