Essential Tools: What to Learn and How
The EDA tools to learn, in what order, and a quick start that runs a full RTL to GDSII flow with OpenLane.
Industry EDA tools such as Design Compiler, Innovus, PrimeTime and Calibre need expensive licences, so students rarely have access. Hiring managers know that. What they want to see is that you understand the concepts and have done real hands-on work with the free equivalents.
Industry tools and their free equivalents
| Domain | Industry Tool | Free/Open Alternative | How to Practice |
|---|---|---|---|
| Synthesis | Synopsys DC / Cadence Genus | Yosys (open source) | Synthesize your Verilog designs with Yosys. Understand liberty files. Write SDC constraints manually. Compare area reports. |
| Place & Route | Cadence Innovus / Synopsys ICC2 | OpenROAD via LibreLane (OpenLane 2 successor) | Use OpenLane with Sky130 PDK. Run full RTL-to-GDS on a small design (UART, I2C, simple CPU). Examine each output. |
| STA | Synopsys PrimeTime / Cadence Tempus | OpenSTA (inside OpenLane) | Read timing reports from OpenSTA. Understand slack calculation. Introduce timing violations manually and fix them. |
| Simulation | Synopsys VCS / Cadence Xcelium / Siemens Questa | Verilator / Icarus Verilog | Write testbenches. Simulate your RTL. View waveforms in GTKWave. Practice writing self-checking testbenches. |
| Physical Verification | Calibre DRC/LVS | Magic VLSI / KLayout | Open Sky130 GDS in KLayout. Inspect metal layers. Run built-in DRC checks. Understand what each layer represents. |
| Parasitic Extraction | Calibre xRC / Synopsys StarRC | OpenRCX (inside OpenROAD) | Run OpenRCX on a placed-and-routed design. Examine the SPEF output. Understand how RC values affect timing. |
| Waveform Viewing | Synopsys Verdi / Cadence SimVision | GTKWave | View VCD dumps from Verilator/Icarus simulation. Practice reading waveforms, adding cursors, measuring timing. |
| Layout Editing | Cadence Virtuoso / Synopsys Custom Compiler | Magic VLSI / KLayout | Draw simple standard cells in Magic. Understand how transistors form. See the connection between schematic and layout. |
The concepts transfer almost one to one. A timing report from OpenSTA reads like one from PrimeTime, and a floorplan in OpenROAD uses the same ideas as one in Innovus. What changes is the command syntax, which every engineer looks up anyway.
Order of learning
- Linux shell and a text editor. Everything else runs there.
- A simulator (Icarus Verilog or Verilator) with GTKWave, for your own RTL.
- Yosys for synthesis, so you see what your RTL turns into.
- LibreLane (the maintained successor of OpenLane 2) for the full flow, including OpenROAD, OpenSTA, Magic, KLayout and Netgen.
- Tcl and Python for reading reports and automating runs.
Quick start: RTL to GDSII with LibreLane
LibreLane is the renamed, actively maintained continuation of OpenLane 2. The simplest install is its official AppImage: one file that contains LibreLane and every tool it drives. The example below runs a small design end to end on the Sky130 open PDK.
# Install LibreLane (one AppImage file with every tool) and enter it
curl -L -o ~/librelane-devshell-x86_64.AppImage \
https://github.com/librelane/librelane/releases/download/3.0.16/librelane-devshell-x86_64.AppImage
chmod a+x ~/librelane-devshell-x86_64.AppImage
~/librelane-devshell-x86_64.AppImage # the prompt becomes [nix-shell:~]$
librelane --smoke-test # the first run downloads the Sky130 PDK
# A minimal design configuration
mkdir -p my_alu/src && cd my_alu # put your alu.v in src/
cat > config.json << 'EOF'
{
"DESIGN_NAME": "my_alu",
"VERILOG_FILES": ["dir::src/alu.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10,
"FP_CORE_UTIL": 40,
"PL_TARGET_DENSITY_PCT": 50
}
EOF
# Run the full flow: synthesis, floorplan, placement, CTS, routing, signoff
librelane --run-tag first config.json
# Each step writes a numbered folder under runs/first/
# Final views (netlist, DEF, GDS, SPEF, metrics) are in runs/first/final/
# Open the result in KLayout
librelane --last-run --flow openinklayout config.jsonClock period is in nanoseconds, so 10 means 100 MHz. After the run, read the timing, DRC and LVS summaries in the final reports and make sure you can explain each number. Then tighten the clock until timing fails, and work out why.
The project that impresses most is not the biggest one, it is the one you understand completely. A small design with a clean run and a story about the one problem you had to solve is enough to fill a technical interview.
Finished reading?
Mark it complete to track your progress through the path.
Go further
Get the full 6-month fresher roadmap, the tool order and a 16-week study plan.
Get new lessons by email
New lessons, interview prep and real EDA tool workflows. No spam.