Wires, Regs, and the Four Values
wire vs reg, 0/1/x/z, and vectors
Signals in Verilog do not just hold 0 or 1. They can hold four values, and knowing them saves you hours of confusion.
| Value | Means | Everyday picture |
|---|---|---|
| 0 | Logic low | Switch off, no voltage |
| 1 | Logic high | Switch on, full voltage |
| x | Unknown | We genuinely do not know - could be 0 or 1 |
| z | High impedance | Wire not connected to anything (floating) |
When a simulation shows x, it is not an error message - it is the tool honestly telling you "this wire was never given a value." That is a clue, not noise.
wire vs reg - the question every beginner asks
These are just two kinds of storage for signals, and the rule for which to use is mechanical once you learn it.
| Type | What it is | Use it when... |
|---|---|---|
| wire | A plain connection, must be continuously driven | You assign it with assign, or connect it between modules |
| reg | A variable that holds its value until changed | You assign it inside an always block |
The name "reg" is misleading. A reg is NOT always a hardware register or flip-flop. It is just a variable you are allowed to assign inside an always block. Whether it becomes a flip-flop depends on HOW you write that block, which you will learn in lesson 7. For now: assign goes with wire, always goes with reg.
Buses - more than one bit
Real signals are often several bits wide (a number, an address). You declare the width with a range in square brackets.
wire [7:0] data; // an 8-bit bus, bits 7 down to 0
reg [3:0] count; // a 4-bit value (holds 0 to 15)
// [7:0] means the most significant bit is bit 7,
// the least significant bit is bit 0. This is the
// normal, recommended order.Writing numbers
4'b1010 // 4 bits, binary -> decimal 10
8'hFF // 8 bits, hex -> decimal 255
8'd255 // 8 bits, decimal -> 255
1'b0 // a single 0 bit
// format is: <width>'<base><value>
// b = binary, h = hex, d = decimal, o = octalIf you forget the width and just write 255, Verilog assumes a 32-bit number. Mixing widths silently is a real source of bugs. Be explicit about width whenever it matters.
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