Synopsys Design Compiler (DC)
The Design Compiler flow: libraries, read/elaborate, constrain, compile_ultra, report and write out; topographical mode and Fusion Compiler.
Synopsys Design Compiler (DC) is the long-established RTL synthesis tool and, for many teams, the reference for what synthesis QoR should look like. Its headline command, compile_ultra, runs elaboration, logic optimisation, mapping and incremental optimisation in one go. DC in topographical mode (and its successor, Fusion Compiler) adds a coarse placement during synthesis so the timing estimates account for real wire delays, not just fanout.
The Design Compiler flow
Point target_library / link_library at the .db cell libraries for your node and corner.
read_verilog (or analyze + elaborate) to bring in the RTL, then link to resolve the hierarchy.
Source the SDC: create_clock, set_input_delay / set_output_delay, and any exceptions.
compile_ultra (add -gate_clock for automatic clock gating, -spg for placement-aware synthesis).
report_qor / report_timing / report_power, then write the netlist and write_sdc for physical design.
set target_library sky130_tt.db
set link_library "* sky130_tt.db"
read_verilog rtl/*.v
current_design top ; link
source constraints.sdc
compile_ultra -gate_clock
report_qor > rpt/qor.rpt
write -format verilog -hierarchy -output netlist/top.v
write_sdc netlist/top.sdcDC concepts worth knowing
- compile_ultra vs compile: compile_ultra is the modern, higher-effort flow (better restructuring, datapath and DRC handling); plain compile is legacy.
- Topographical / DCT mode: synthesis with an internal placement so wire-load estimates are physical, closing the RTL-to-layout correlation gap.
- .db is the compiled binary form of the .lib timing library; .ddc is DC’s own design database format.
- Fusion Compiler is Synopsys’ newer single-tool RTL-to-GDS engine that shares DC’s synthesis core.
| Command | Purpose |
|---|---|
| read_verilog / analyze + elaborate | Read and build the design from RTL |
| link | Resolve references across the hierarchy |
| create_clock / set_input_delay / set_output_delay | Define timing constraints (SDC) |
| compile_ultra | Run the full synthesis + optimisation flow |
| report_qor / report_timing / report_power | Check timing, area and power |
| write / write_sdc | Emit the gate-level netlist and forwarded constraints |
In short, Design Compiler is the classic synthesis engine: set libraries, read and constrain the RTL, compile_ultra, then report and hand the netlist plus SDC to physical design.
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