Formula Cheatsheet

⏱ Setup Timing

Slack_setup = T_req - T_arr

T_req = Period + T_clk_capture - T_uncertainty - T_setup

T_arr = T_clk_launch + T_cq + T_combo

Positive slack = PASS, Negative = FAIL

⏳ Hold Timing

Slack_hold = T_arr - (T_clk_cap + T_hold)

T_arr must be GREATER than capture clock + hold time

Fix: Add delay buffers to data path

Floorplan

Util = CellArea / CoreArea × 100%

AR = CoreHeight / CoreWidth

CoreArea = CellArea / Util_target

Target utilization: 60-75%

IR Drop

V_drop = I × R_metal

R = ρ × L / (W × T)

Max allowed: typically 5-10% of VDD

Fix: wider stripes, more stripes, decaps

Electromigration

J = I / A (current density)

J_max = A × e^(-Ea/kT)

Black's equation for MTTF. Wider wires → lower J

Clock Skew

Skew = T_clk_cap - T_clk_launch

Positive: relaxes setup, tightens hold

Negative: tightens setup, relaxes hold

Dynamic Power

P_dyn = α × C × V² × f

α = activity factor, C = load cap, V = supply, f = frequency

Leakage Power

P_leak ∝ W/L × e^(-Vt/nVT)

Exponential sensitivity to Vt. HVT cells reduce leakage

WNS / TNS

WNS = min(all slacks)

TNS = Σ(negative slacks)

WNS → worst path. TNS → total work needed.

PVT Corners

Setup: SS, low V, high T

Hold: FF, high V, low T

Temperature inversion at <65nm nodes!

Wire Delay (Elmore)

T_d = 0.69 × R × C

T_d ∝ L² (wire delay scales as L²)

Long wires need repeaters/buffers every Lopt

Fanout & Buffering

Logical Effort: g = C_in / C_inv

Optimal fanout = e ≈ 2.7 (e-based)

Buffer chain for high-fanout: h = C_load/C_in, stages = log_e(h)