SystemVerilog for Verification

Designs are written in Verilog or SystemVerilog. Testbenches use the richer features of SystemVerilog - the parts built specifically for verification. You do not need all of it at once; here are the pieces you will use constantly.

logic - the type to default to

In testbenches, just use logic for almost everything. It replaces the old wire vs reg headache - logic can be driven both ways, so you stop worrying about which to pick.

Containers that grow

int   q[$];          // a queue
q.push_back(5);      // add to the end
q.push_back(9);
int x = q.pop_front(); // take from the front -> 5

int mem[int];        // associative array (dictionary)
mem[1000] = 42;      // store 42 at address 1000

Tasks and functions

• function - returns a value, takes no time (no delays). Use for calculations like an expected result.
• task - can consume time (delays, waits). Use for sequences of actions like "drive this, wait a clock, drive that."

Interfaces - bundle the wires

Instead of passing a dozen separate signals everywhere, an interface bundles related wires into one named group. It keeps connections clean as the design grows, and it is the standard way testbenches connect to a DUT.

interface bus_if (input logic clk);
  logic        valid;
  logic [7:0]  data;
endinterface

// Now a whole bus is passed as one thing, not 3 signals.