Boundary Scan and JTAG

Scan tests inside a chip, MBIST tests its memories. Boundary scan tests the connections between chips on a board, and it is also how you access most on-chip test features. It is defined by the IEEE 1149.1 standard, usually just called JTAG.

The problem it solves

Once chips are soldered onto a board, you cannot reach the pins with probes to check that every solder joint and trace is good. Boundary scan adds a register cell at each chip pin so that, in test mode, you can drive and observe every pin through a small standard interface, checking the board connections without physical probes.

The boundary scan register

Each input and output pin gets a boundary scan cell. Chained together, these cells form a shift register around the edge of the chip. You shift a pattern out onto the output pins of one chip and capture what arrives at the input pins of the next, which proves the board-level wiring between them is intact.

The TAP - the standard access port

JTAG defines a Test Access Port: a small set of pins (TCK clock, TMS mode, TDI data in, TDO data out, and optional TRST reset) and a state machine that controls test operations. This same port has become the universal way to get at a chip internal test and debug features, far beyond its original board-test purpose.